Digital Storage TRIZ Cases

Correlated electron switches reduce voltage stress and extend endurance by performing selective writes only when data differs.

A multi-mode array structure integrates memory cells with function lines to enable TCAM, CNN, and SNN operations within a single in-memory computing unit.

A semiconductor memory apparatus uses a synchronous delay circuit unit to generate bank write enable signals synchronized with column active pulses.

Error correction circuit detects read data faults before masked write operations to generate new write data.

Easy cone anisotropy in the free layer reduces write error rates and improves thermal stability for scalable spin transfer torque random access memory.

Segmented free layers with distinct magnetic moments balance low switching current against high data retention via magnetic exchange coupling.

Floating word lines during operations detects voltage shifts from leakage currents, preventing unrecoverable data loss caused by progressive defects.

A driving method applies distinct voltage pulses to variable resistance layers to control resistance states.

Parallel transistor-MTJ branches in a 3T4M STT-MRAM cell boost read-write speeds while shrinking layout area.

A shared integrated regulator isolates accessed SRAM sub-banks from non-accessed ones to maintain stable sleep voltage levels.

Alternating voltage pulses recover residual polarization in unselected ferroelectric memory cells, suppressing data loss from disturbance effects.

A sense amplifier circuit uses a dedicated voltage regulator to generate a reference voltage below Vdd for reliable data sensing operations.

Sequential bank activation and word line selection reduce current consumption while maintaining refresh coverage in semiconductor memory devices.

An asymmetric memory cell array suppresses half-selected current contamination to maintain consistent voltage drops during scaling.

A control circuit calculates median water levels to synchronize asynchronous data exchange between write and read circuits.

A diode-connected buffer reduces signal swing on capacitive lines to lower dynamic power consumption.

A semiconductor memory device detects bridge defects between adjacent memory cells using a segmented sense amplifier operation.

VSSB coupling device eliminates gate-source cross voltage to reduce leakage currents and power consumption.

Dynamic current limiter reduces voltage during RRAM programming to prevent overstress conditions and improve data retention.

An internal timer in the word line cache mode disconnects driver voltages early, reducing channel hot carrier and gate-induced drain leakage stress.

A semiconductor storage device allocates local word lines between normal and redundancy cell arrays using inverted selection signals.

A control unit generates a voltage difference between data strobe signals to prevent signal glitches.

A column address counter circuit uses a mask clock to increment the most significant bit of addresses.

A read control signal generating unit determines the minimum frame period from multiple video sources to drive a DDR memory controller.

A row hammer management circuit counts access frequencies to identify victim rows and triggers targeted refresh operations.

A semiconductor memory apparatus uses a capacity control circuit to restrict power and signals to residual regions.

Asymmetric channel layers eliminate inverters to reduce memory cell area and circuit complexity.

A storage medium processing module compares access data with verify data to generate a report.

A neuromorphic synapse apparatus uses programming logic to exploit memelement characteristics for weight-dependent synaptic update efficacy.

A wiring substrate integrates common mode choke coils into differential transmission lines to shorten clock wire lengths while maintaining signal integrity.

Clamping voltage drops across magnetic tunnel junctions reduces parasitic capacitance delays and halves access time.

A read buffer transistor mediates bit line access to prevent data flip in half-selected SRAM cells.

Pre-discharged bit lines reduce DC and AC power consumption in multi-port SRAM by minimizing voltage swings during read operations.

Segmenting the cell array into discharge and precharge zones reduces current leakage while maintaining high access speed.

Ring address latch adjusts stage count to burn row and column failed addresses concurrently, eliminating separate clock cycles for testing.

State machine and register control circuitry enables parallel column access in SRAM to reduce clock cycles required for multi-bitcell operations.

Tri-state memory cells store ternary voltage levels to increase storage density beyond binary limits.

A memory circuit decoder uses an address control signal buffer to convert signals into inverted forms for stable cell selection.

In-band register update modes configure memory devices using command and address bus signals, bypassing slow sideband buses to accelerate training.

Segmented test circuitry controls wordline, array, and bitline voltages independently to identify specific failure types during SRAM testing.

A data write-in method adjusts reset and set voltages based on verification currents to optimize memory cell operations.

Segmenting the pipe latch circuit into parallel phases maintains high output speed and low latency despite increased storage capacity.

A three-port SRAM circuit enables synchronous reading from ports B and C through dedicated bit lines and transistors.

A signal delay buffer coordinates multiple smaller memory circuits to expand storage capacity while resolving synchronization complexity.

Merging multiple smaller CAMs into one unified array shares decoders and registers, reducing area and power consumption while maintaining performance.

A resistive memory operating method measures leakage current to adjust inhibit voltages across the cell array.

A 3D stacked architecture with compute-in-memory modules and vertical routers.

A row decoder circuit uses a global predecoding stage to generate high-voltage address signals.

A stabilizing pulse locks programmed resistance states within target ranges to prevent spontaneous drift.

A 2T0C memory cell design uses a vertical gate transistor to replace the capacitor component.