Diode-Connected Buffer Voltage Scheme for DRAM Signal Integrity
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Solution Overview
Problem
Highly capacitive interconnect lines in semiconductor integrated circuits face challenges in operating at high speeds without significant increases in dynamic power consumption and internal supply voltage degradation, particularly in DRAMs where global IO lines are critical and extend over long distances.
Innovation Solution
The implementation of a circuit with tri-state buffers and diode-connected transistors that utilize a lower power supply voltage to reduce signal swing on highly capacitive lines, minimizing power consumption and improving signal integrity and propagation speed by limiting the active state of tri-state buffers to only when data is available, and using diodes to drop the power supply voltage and ensure stable current delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high speed switching is implemented on highly capacitive interconnect lines, then operating speed is improved, but dynamic power consumption increases significantly
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced power supply voltage (VDD - Vdiode) for buffers driving highly capacitive interconnect lines. This voltage reduction directly decreases the energy consumed during switching operations while maintaining adequate signal swing for reliable data transmission at high speeds.
Solution Approach 2:
The patent applies different power supply voltages to different parts of the circuit: full voltage VDD for receiving circuits and reduced voltage (VDD - Vdiode) for buffers driving highly capacitive lines. This localized quality adjustment optimizes power consumption specifically where needed without compromising overall system performance.
2Speed
If high speed switching is implemented on highly capacitive interconnect lines, then operating speed is improved, but internal supply voltage degradation worsens
Solution Approach 1:
The patent introduces a reduced voltage parameter (VDD - Vdiode) for buffers driving highly capacitive lines, which decreases the current demand and reduces voltage drops on internal power supply networks. This parameter change stabilizes internal supply voltages during high-speed operations.
Solution Approach 2:
The diode-connected transistor acts as an intermediary voltage regulation element between the main power supply VDD and the buffer power supply. It automatically adjusts the buffer voltage based on current demand, preventing excessive current draws that would cause supply voltage degradation.
3Reliability
If proper buffering and sizing of driver circuits is implemented, then signal integrity is improved, but power consumption increases
Solution Approach 1:
The patent optimizes the power supply voltage parameter for driver buffers by reducing it to (VDD - Vdiode), which decreases power consumption while maintaining sufficient voltage swing for reliable signal transmission. The diode ensures the voltage remains stable and appropriate for the buffering function.
Solution Approach 2:
The patent applies reduced power supply voltage specifically to buffers driving highly capacitive interconnect lines, while other circuits continue to operate at full voltage. This localized adjustment maintains signal integrity where needed while reducing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and internal supply voltage degradation while enhancing signal propagation speed and integrity by limiting signal swing and optimizing power supply voltage usage, effectively addressing the challenges of high capacitive interconnect lines in semiconductor ICs.
Implementation Method 1
Each of the plurality of buffers may be coupled to a power supply voltage through a corresponding diode
Data Source
AI summary
A circuit includes a plurality of buffers configured to provide data on a corresponding signal line. Each of the plurality of buffers may be coupled to a power supply voltage through a corresponding diode. A plurality of receiving circuits may be coupled to receive the data provided on a corresponding one of the plurality of signal lines. The plurality of receiving circuits may be directly powered by the power supply voltage.