E-fuse Burning Circuit Concurrent Row Column Address Latch

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Solution Overview

Problem

Conventional memory testing requires two stages and cannot concurrently burn row and column failed addresses with different directions, leading to low throughput due to the need for separate clock signal cycles.

Innovation Solution

An E-fuse burning circuit and method that includes a burning directing circuit, a ring address latch, and a control signal generating circuit to generate signals for concurrently burning row and column failed addresses by adjusting the number of stages for output based on the direction of the failed address.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If row failed addresses and column failed addresses are burned in separate clock signal cycles, then the burning process can be completed accurately, but the throughput rate is low and the testing time is extended

Engineering Contradiction:
Improveburning accuracyVSAvoidthroughput rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the burning processes for row failed addresses and column failed addresses into a single clock signal cycle by using a ring address latch that can simultaneously generate both row address output signals and column address output signals. This combining of previously separate operations resolves the contradiction by achieving both accurate burning and high throughput rate.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ring address latch employs dynamic control through a burning directing signal that can switch the latch between different operating modes: generating row address outputs, generating column address outputs, or generating both simultaneously. This dynamic adaptability allows the system to maintain burning accuracy while maximizing throughput by concurrent operation.

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If a conventional testing process is used with separate stages for row and column testing, then the testing can be completed systematically, but the testing time is extended and efficiency is reduced

Engineering Contradiction:
Improvetesting systematizationVSAvoidtesting time
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The patent implements continuous useful action by enabling the ring address latch to continuously generate address outputs for both row and column burning operations within the same clock cycle without interruption or sequential waiting. This eliminates idle time between row and column testing stages while maintaining systematic testing procedures.

Inventive Principle:
Principle #20Continuity of useful action

3Device complexity

If the ring address latch applies a fixed number of stages, then the circuit design is simple, but it cannot adapt to different burning directions (row or column)

Engineering Contradiction:
Improvecircuit designVSAvoidburning direction adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The ring address latch is designed as a universal component that can perform multiple functions: it can generate row address outputs, column address outputs, or both simultaneously based on the burning directing signal. This multi-functionality allows a single fixed-stage latch to adapt to different burning directions without requiring separate circuits for each case.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the ring address latch through control signals rather than altering its physical structure. By modifying the burning directing signal and control signal generating circuit inputs, the same fixed-stage latch can adapt its behavior to match different burning directions (row or column) without requiring structural modifications.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10672495B1E-fuse burning circuit and E-fuse burning method
Publication Date: 2020.06.02 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
  • US10672495B1 patent drawing
  • US10672495B1 patent drawing
  • US10672495B1 patent drawing

AI summary

An E-fuse burning circuit comprising: a burning directing circuit, configured to receive first input data comprising first input address and burning directing data, to generate a burning directing signal according to the burning directing data; a ring address latch, configured to latch the first input address responding to a first clock signal, and configured to output second input address responding to the first clock signal; and a control signal generating circuit, configured to generate at least one stop signal to determine whether the data in the ring address latch is shifted or not. The ring address latch applies a first number of the stages when the burning directing signal indicates a row of the E-fuse circuit is to be burned and applies a second number of the stages when the burning directing signal indicates a column of the E-fuse circuit is to be burned.