Column Address Counter Circuit for Accurate Counting

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Solution Overview

Problem

Existing column address counter circuits in semiconductor memory devices face challenges in securing an adequate margin for count operations, especially when the cycle of the count clock is short, leading to improper counting of column addresses.

Innovation Solution

A column address counter circuit that includes a clock mask unit to generate a mask clock toggled by a set number of internal clock times, a clock state unit to set next mask and state based on decoded address signals, and a column address counter unit to generate column addresses by counting the internal clock, with the most significant bit increased in response to the mask clock, ensuring proper counting margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the count clock cycle is shortened to increase operating speed, then productivity is improved, but the column address counter cannot complete counting operations properly, worsening reliability

Engineering Contradiction:

Improveoperating speedVSAvoidcounting accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The column address counter is divided into two independent counter units: a first counter unit that counts column addresses at every clock cycle, and a second counter unit that counts only at rising edges. This segmentation allows each counter to operate independently with appropriate timing, resolving the conflict between high-speed operation and accurate counting completion.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first counter unit performs preliminary counting of all column addresses at every clock cycle, preparing the count results in advance. The second counter unit then selects and outputs the appropriate count results based on rising edge timing. This preliminary action ensures that counting is completed before output, maintaining reliability even with short clock cycles.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the count operation margin is increased to ensure accurate counting, then reliability is improved, but the operating speed decreases, worsening productivity

Engineering Contradiction:

Improvecounting accuracyVSAvoidoperating speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system dynamically switches between two counting modes: the first counter operates at full clock speed for continuous counting, while the second counter synchronizes with rising edges for output. This dynamic operation allows the system to maintain high operating speed while ensuring accurate counting completion at critical timing points.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The first counter unit continuously counts column addresses at every clock cycle without interruption, maintaining continuous useful action. The second counter unit continuously monitors rising edges and outputs appropriate results. This continuous operation eliminates idle time and maintains high productivity while ensuring reliability.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8854917B2Column address counter circuit of semiconductor memory device

Publication Date: 2014.10.07 SK HYNIX INC

AI summary

The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.