Sense Amplifier Reference Voltage Regulation for Memory Sensing
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Solution Overview
Problem
Existing dynamic memory circuits face challenges in achieving reliable high-speed sensing operations without requiring dummy cells or additional write select signals, which increases silicon area and leads to cell disturb errors and reduced packing density.
Innovation Solution
A sense amplifier circuit with a separate read and write path from global bit lines to local bit lines, using an on-chip voltage regulator to provide a reference voltage less than Vdd, and a three-stage voltage regulator circuit to improve performance, allowing for full Vdd precharge with a reference voltage of approximately 80% of Vdd for sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy cells are used to provide reference voltage for sensing, then sensing reliability is improved, but silicon area increases and packing density decreases
Solution Approach 1:
The patent extracts the reference voltage generation function from traditional dummy cells and implements it using a dedicated voltage regulator circuit. This regulator circuit generates a reference voltage (Vref) that is less than Vdd, providing the necessary reference level for sensing operations without requiring additional dummy memory cells, thereby reducing silicon area while maintaining sensing reliability
Solution Approach 2:
The patent changes the voltage parameter by using a regulated reference voltage (Vref < Vdd) instead of relying on dummy cells to provide reference levels. The voltage regulator circuit dynamically adjusts and maintains the reference voltage at an appropriate level for sensing, eliminating the need for dummy cells and improving packing density
2Reliability
If additional write select signals are used to prevent cell disturb errors, then reliability is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent removes the need for additional write select signals by using a separate read and write path architecture. The write operation uses a different signal path controlled by write enable signals, isolating write operations from sense operations and preventing cell disturb errors without requiring extra select signals, thus reducing device complexity
Solution Approach 2:
The patent segments the bit line interface into separate read and write paths. The write path is controlled by write enable signals and operates independently from the sense amplifier path, allowing write operations to occur without interfering with sensing operations, thereby preventing cell disturb errors while maintaining simple control logic
3Speed
If full Vdd precharge is used with reference voltage less than Vdd, then sensing speed is improved, but voltage regulation complexity increases
Solution Approach 1:
The patent uses a three-stage voltage regulator circuit that efficiently regulates the reference voltage to be less than Vdd. This enables full Vdd precharge on bit lines while maintaining an appropriate reference voltage level for sensing, achieving high-speed sensing operations. The regulator circuit uses standard CMOS transistors and requires minimal external components, keeping the implementation relatively simple despite the voltage regulation function
Data Source
AI summary
A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.