Tri-State Memory Cells Increase Density via Ternary Voltage Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices using binary memory cells are limited in memory density and layout flexibility, as they require one memory cell and one bit line per bit of memory capacity, whereas tri-state memory cells can store one of three voltage levels, allowing for increased density and different geometries.
Innovation Solution
The implementation of tri-state memory cells that translate between three binary values and two voltage levels, enabling 50% greater memory density and allowing for various layouts and geometries by using two memory cells and two bit lines per three bits of memory capacity, along with logic to manage these translations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If binary memory cells are used, then the memory device structure is simple and easy to manufacture, but the memory density is limited to one bit per memory cell
Solution Approach 1:
The patent changes the fundamental parameter of memory cell capacity from binary (2 states) to ternary (3 states) by utilizing three distinct voltage levels (first voltage, second voltage, and third voltage) instead of just high and low voltages. This parameter change enables each memory cell to store one of three possible values, achieving 50% higher memory density without requiring a complete redesign of memory architecture
Solution Approach 2:
The patent segments the voltage representation into distinct categories: first voltage level representing first binary value, second voltage level representing second binary value, and third voltage level representing third binary value. This segmentation of voltage states allows for systematic encoding and decoding of ternary data, resolving the complexity of implementing multi-state memory cells
2Adaptability or versatility
If binary memory cells are used, then the bit line configuration is straightforward (one bit line per bit), but the layout flexibility and geometry options are limited
Solution Approach 1:
The patent implements multi-functionality in bit line configuration where bit lines can be shared between multiple memory cells. Specifically, two bit lines can serve three memory cells, and three bit lines can serve four memory cells, depending on the selected voltage levels. This universal usage pattern provides multiple layout configurations and geometric arrangements, significantly enhancing layout flexibility
Solution Approach 2:
The patent introduces dynamic configuration capabilities where the bit line assignment can vary based on operational requirements. The system can dynamically adjust which bit lines are active and how they map to memory cells, enabling flexible layout adaptations for different memory capacity and configuration needs without hardware redesign
3Productivity
If tri-state memory cells are implemented, then memory density increases to 50% greater capacity, but translation logic between binary and ternary values is required
Solution Approach 1:
The patent introduces translation logic as an intermediary component that mediates between binary input/output signals and ternary memory cell states. This intermediary layer handles the conversion between binary values (0 and 1) and ternary voltage levels (first, second, and third voltages), enabling the memory device to interface with conventional binary systems while maintaining enhanced storage capacity
Solution Approach 2:
The translation logic incorporates feedback mechanisms to accurately detect and interpret voltage levels from memory cells during read operations, and to properly set voltage levels during write operations. This feedback ensures reliable bidirectional translation between binary and ternary representations, managing the complexity through systematic control
4Area of moving object
If conventional binary memory cells are used, then the device size for a given capacity is larger, but the manufacturing process is simpler
Solution Approach 1:
The patent merges multiple binary memory cell functions into a single ternary memory cell. Each ternary cell can store the equivalent information of 1.5 binary cells, effectively merging the storage capacity of multiple cells into fewer, more efficient units. This merging reduces the total number of memory cells required and consequently decreases the overall device area while maintaining or improving manufacturing efficiency
Data Source
AI summary
Memory devices including tri-state memory cells are disclosed. A memory device may include a first tri-state cell that may store a first voltage level that is one of three voltage levels, a second tri-state cell that may store a second voltage level that is one of the three voltage levels, and three input/output lines that may access the memory device. The three input/output lines may carry three respective binary signals based on the first voltage level and the second voltage level. A memory device may include a bank including a number of continuous arrays of tri-state memory cells. Each of the tri-state memory cells may be accessible by a respective bit line. Groups of the bit lines may be associated with respective column-select lines. The bank may include a number of sub-word-line drivers interspersed between the number of continuous arrays. Associated systems and methods are also disclosed.