Semiconductor Storage Redundancy Allocation via Inverted Signals
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Solution Overview
Problem
Semiconductor storage devices face challenges in efficiently managing defective memory cells within their arrays, particularly in allocating and utilizing redundancy to maintain performance and yield, as existing solutions often require complex circuitry and may not effectively handle defects across different rows and columns.
Innovation Solution
The semiconductor storage device incorporates a redundancy controller and column/select circuits that dynamically allocate local word lines between normal and redundancy cell arrays based on row and column redundancy signals, allowing for efficient defect management by inverting redundancy signals to select appropriate sub-arrays for normal or redundancy operations, thereby minimizing circuit area and enhancing repair efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuitry is used to manage defective memory cells, then defect management capability is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own local redundancy resources. This segmentation allows defect management to be handled at the sub-array level rather than requiring complex global management circuitry, reducing overall device complexity while maintaining reliable defect management capability
Solution Approach 2:
Redundancy cells are pre-configured and mapped to specific sub-arrays before operation. The redundancy controller maintains mapping information that enables quick allocation of redundancy resources when defects are detected, eliminating the need for complex real-time defect management circuitry
2Productivity
If redundancy signals are inverted to select appropriate sub-arrays, then repair efficiency is improved, but control complexity increases
Solution Approach 1:
The redundancy control mechanism inverts the selection logic by using inverted redundancy signals to select appropriate sub-arrays for normal or redundancy operations. This inversion simplifies the control mechanism by leveraging the natural complementarity of selection states, improving repair efficiency without significantly increasing control complexity
3Adaptability or versatility
If local word lines are dynamically allocated between normal and redundancy cell arrays, then defect management flexibility is improved, but circuit area increases
Solution Approach 1:
Local word lines are designed to serve dual purposes: they can activate memory cells in normal cell arrays during regular operation or activate redundancy cells during defect management operations. This multi-functionality provides defect management flexibility without requiring separate dedicated circuitry, thus avoiding significant increases in circuit area
Solution Approach 2:
The allocation of local word lines between normal and redundancy cell arrays is dynamically controlled based on defect detection and repair needs. The redundancy controller can reconfigure word line connections on-the-fly, providing adaptability while using the same physical circuit resources, thereby minimizing additional circuit area requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-quality semiconductor storage devices with improved defective memory cell repair efficiency while keeping circuit complexity low, allowing for simultaneous normal and redundancy operations with efficient allocation of redundancy areas.
Implementation Method 1
An MTJ (Magnetic Tunnel Junction) element of the spin transfer torque write method has a multilayered structure including two ferromagnetic layers and a nonmagnetic barrier layer (thin insulating film) sandwiched between them, and stores digital data by the change in magnetic resistance caused by the spin polarization tunneling effect.
Implementation Method 2
Write methods of the MRAM are a magnetic field write method and spin transfer torque write method. The spin transfer torque write method has a property by which as the size of a magnetic material decreases, a spin transfer torque electric current required for magnetization switching reduces.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first storage area including a plurality of memory cells each including a resistance change element which stores data; a second storage area including a plurality of memory cells each including a resistance change element which stores data; a sub memory cell array including the first storage area and the second storage area: a memory cell array including a plurality of sub memory cell arrays arranged along a column direction and a row direction; a third storage area which stores redundancy information and to supply the redundancy information to the sub memory cell array; and a control circuit which controls an access operation to the memory cell array.