Low Power Single-Ended SRAM Sensing with Pre-Discharged Bit Lines
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Solution Overview
Problem
Multi-port SRAM cells face high DC and AC power consumption due to current leakage and bit line voltage swings, which increases with SRAM cell density, and existing techniques to reduce leakage either increase area or decrease performance.
Innovation Solution
The SRAM read port bit lines are pre-discharged to zero volts when not accessed, and only energized to an intermediate voltage when accessed, using high threshold voltage NFET switches to minimize current leakage and voltage swings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are continuously pre-charged to high voltage to enable fast reading, then reading speed is improved, but DC power consumption increases due to current leakage
Solution Approach 1:
The patent applies periodic action by pre-charging bit lines only during active read operations rather than continuously. The circuit uses a pre-charge transistor that is activated only when a read operation is detected, allowing the bit line to be charged to high voltage temporarily for fast reading, then discharged to low voltage to eliminate continuous leakage current, thus resolving the contradiction between reading speed and DC power consumption
Solution Approach 2:
The patent uses preliminary action by pre-charging the bit line to high voltage immediately before a read operation occurs. This preliminary pre-charge ensures the bit line is ready for fast data transfer when the read operation starts, while the pre-charge transistor is subsequently turned off to eliminate continuous power consumption, addressing both speed and power concerns
2Area of stationary object
If single-ended read port structure is used to reduce area, then area efficiency is improved, but sensing capability deteriorates due to inability to use common sense amp detection
Solution Approach 1:
The patent introduces an intermediary differential sensing circuit that converts the single-ended bit line signal into a differential signal suitable for common sense amp detection. The circuit includes a dummy bit line and sensing transistors that create a differential pair, allowing the single-ended read port to utilize robust common sense amp detection circuits while maintaining area efficiency, thus resolving the contradiction between area and sensing capability
3Quantity of substance
If SRAM cell density is increased to improve capacity, then memory capacity is improved, but power consumption increases due to increased leakage current
Solution Approach 1:
The patent applies periodic action by implementing dynamic pre-charge control where the pre-charge transistor is activated only during active read operations rather than continuously. This allows high-density SRAM cells to maintain fast read capability when needed while eliminating continuous leakage current from constantly pre-charged bit lines, thus resolving the contradiction between memory capacity and power consumption
Data Source
AI summary
An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.