Word Line Cache Mode Mitigates CHC and GIDL Stress
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Solution Overview
Problem
Modern memory devices face performance issues due to channel hot carriers (CHC), row address strobe (RAS) clobber, and gate-induced drain leakage (GIDL) in word line drivers, caused by increased voltages and close proximity of word lines, leading to capacitance-based performance problems and power inefficiencies.
Innovation Solution
Implementing a cache mode that applies local controls to reduce direct external control over word lines, using timers and dynamic voltage adjustments to mitigate CHC, RAS clobber, and GIDL by controlling voltage duration and magnitude, thereby reducing stress on transistors and adjacent word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If increased voltages are applied to word line drivers to improve performance, then speed of operation is improved, but channel hot carrier (CHC) issues and gate-induced drain leakage (GIDL) worsen
Solution Approach 1:
The patent implements periodic voltage adjustments by pulsing the word line voltage to specific levels (VWL_PRE, VWL_MAIN, VWL_POST) at different time intervals during the operation cycle. This periodic voltage modulation allows the system to achieve high speed during the main operation phase while reducing voltage stress during transition phases, thereby minimizing CHC and GIDL effects while maintaining operational speed.
2Duration of action of stationary object
If word lines are activated for extended duration to maintain data, then memory retention is improved, but row address strobe (RAS) clobber occurs on adjacent word lines
Solution Approach 1:
The patent applies different voltage levels to different word lines simultaneously based on their operational state. Active word lines receive the main voltage level (VWL_MAIN) for data retention, while adjacent word lines that are not currently active receive reduced voltage levels or remain at ground potential. This localized voltage differentiation maintains data retention on active lines while preventing RAS clobber stress on adjacent inactive lines.
3Strength
If higher voltages are used in word line drivers to overcome capacitance effects, then signal strength is improved, but power efficiency deteriorates due to GIDL
Solution Approach 1:
The patent dynamically adjusts the voltage level on word lines based on the operational phase. During the pre-charge phase, a lower voltage (VWL_PRE) is applied; during the main operation phase, the voltage is increased to (VWL_MAIN) to provide strong signal drive; and during the post-operation phase, the voltage is reduced to (VWL_POST). This dynamic voltage adjustment maintains strong signal strength when needed while minimizing power consumption and GIDL effects during transition and idle phases.
Data Source
AI summary
Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.