Signal Delay Buffer for Memory Capacity Expansion
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Solution Overview
Problem
The increasing memory capacity requirements of computers, particularly servers, are hindered by the reduction in memory module slots due to industry trends like higher memory bus speeds and small form factor machines, while large capacity memory modules are cost-prohibitive, necessitating a cost-effective approach to enhance memory capacity.
Innovation Solution
A system and method that delays signals communicated between a system and multiple memory circuits, using a component to interface with memory circuits and simulate a larger capacity memory circuit, allowing for the use of multiple smaller capacity memory circuits to mimic a single larger capacity memory circuit, thereby increasing overall memory capacity without the high cost of large monolithic modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple smaller capacity memory circuits are used to increase memory capacity, then cost is reduced and memory capacity is increased, but device complexity increases due to the need for additional components and signal delay mechanisms
Solution Approach 1:
A buffer component is introduced as an intermediary between the system and multiple memory circuits. This buffer receives signals from the system, applies appropriate delays to synchronize signals across multiple memory circuits, and then communicates with each memory circuit. The buffer acts as a mediator that manages the complexity of coordinating multiple memory circuits while presenting a simplified interface to the system.
Solution Approach 2:
The memory system is segmented into multiple smaller capacity memory circuits instead of using a single large capacity memory circuit. This segmentation allows the system to achieve the desired total memory capacity while reducing cost, as multiple smaller memory modules can be sourced more economically than one large monolithic memory circuit. The buffer component manages these segmented memory circuits collectively.
2Quantity of substance
If multiple smaller capacity memory circuits are used instead of a single large capacity memory circuit, then cost is reduced, but signal synchronization becomes more difficult due to varying signal propagation times
Solution Approach 1:
The buffer component performs preliminary actions by receiving signals from the system before distributing them to multiple memory circuits. It applies predetermined delay values to each signal based on the specific characteristics of each memory circuit, ensuring that all memory circuits receive synchronized signals at the correct time. This preliminary delay adjustment prevents synchronization issues before they occur.
Solution Approach 2:
The buffer component dynamically adjusts the delay parameter for signals sent to each memory circuit. By changing the delay parameter based on the specific timing requirements of each memory circuit, the system achieves proper signal synchronization across all memory circuits despite their different characteristics and positions in the system.
3Reliability
If a buffer component is introduced to delay and synchronize signals to multiple memory circuits, then signal synchronization is improved, but device complexity and component count increase
Solution Approach 1:
The buffer component is designed to perform multiple functions: it receives signals from the system, determines appropriate delay values based on memory circuit characteristics, applies the delays, and distributes signals to multiple memory circuits. This multi-functionality consolidates what could be multiple separate components into a single universal buffer, reducing overall device complexity while maintaining signal synchronization.
4Device complexity
If large capacity monolithic memory circuits are used, then device complexity is reduced, but cost increases significantly
Solution Approach 1:
Instead of using a single large capacity monolithic memory circuit (the conventional approach), the invention inverts the approach by using multiple smaller capacity memory circuits combined through a buffer. This inversion achieves the desired memory capacity while actually reducing cost, as multiple smaller memory modules are more economically viable than one large expensive monolithic circuit. The buffer manages the complexity that would otherwise result from this inverted architecture.
Data Source
AI summary
A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.