Multi-State Sense Amplifier Voltage Clamping for MRAM
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Solution Overview
Problem
Magnetic Random Access Memory (MRAM) access time is increased due to parasitic capacitance and voltage drops across Magnetic Tunnel Junction (MTJ) devices, which hinder the performance of multi-state sense amplifiers in detecting current levels for data storage.
Innovation Solution
A multi-state sense amplifier is coupled with memory cells and reference cells, utilizing a source follower, source follower circuit, and current mirror circuit to clamp voltages and generate reference voltages, reducing access time by preventing voltage pull-up to a logic high level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-state sense amplifier is used to detect current levels for data storage, then measurement precision is improved, but access time is increased due to parasitic capacitance and voltage drops
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line and reference line to a predetermined voltage level before the sensing operation. This preparation ensures that when the memory cell is accessed, the voltage drops can be quickly and accurately measured without delay, thus improving measurement precision while minimizing access time penalty
Solution Approach 2:
The patent introduces an intermediary mechanism by using a current mirror circuit that mirrors the current from the memory cell through a controlled path. This intermediary current path allows the sense amplifier to detect voltage drops accurately while isolating the parasitic capacitance effects, thereby maintaining measurement precision without significantly increasing access time
2Ease of operation
If the memory cell is directly coupled to the multi-state sense amplifier, then ease of operation is improved, but access time is increased due to voltage drops inducing current flow that cannot immediately charge parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line and reference line to a predetermined voltage level before the sensing operation. This preparation ensures that when the memory cell is accessed, the voltage drops can be quickly and accurately measured without delay, thus improving measurement precision while minimizing access time penalty
Solution Approach 2:
The patent applies preliminary anti-action by using a current mirror circuit that mirrors the current from the memory cell through a controlled path. This intermediary current path allows the sense amplifier to detect voltage drops accurately while isolating the parasitic capacitance effects, thereby maintaining measurement precision without significantly increasing access time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces access time by half and improves MRAM performance by maintaining constant voltage drops across memory and reference cells, enabling efficient data retrieval from MRAM cells with changeable resistance.
Implementation Method 1
The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node
Implementation Method 2
The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thus generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes
Implementation Method 3
A magnetic field applied to the MRAM cell 100 shifts the polarity of the ferromagnetic layers changing the resistance of the MTJ devices 104 and 106. Thus, the MTJ devices 104 and 106 can be switched between two levels of resistance
Data Source
AI summary
The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.