Wiring Substrate Clock Wire Length Reduction via Common Mode Choke Coil
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Solution Overview
Problem
Conventional DDR memory wiring substrates with equal-length wires face challenges in maintaining signal waveform quality at high frequencies and reducing wiring area, as existing chip delay lines tend to attenuate high-frequency signals and increase wiring area due to the need for equal wire lengths.
Innovation Solution
A wiring substrate with equal-length wires that incorporate a common mode choke coil in the differential transmission line, allowing for reduced wire length and elimination of the meander shape, thereby decreasing the wiring area while maintaining signal waveform quality through impedance matching and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If equal-length wires are formed using meander shape to equalize delay times, then signal synchronization is achieved, but wiring area increases
Solution Approach 1:
The patent changes the electrical parameters by introducing common mode choke coils with specific delay times into the differential transmission lines. This allows wires of different physical lengths to achieve equal electrical delay times, eliminating the need for meander shapes and reducing wiring area while maintaining signal synchronization.
2Reliability
If chip delay line with tri-plate structure is used to adjust wire length, then delay time equalization is achieved, but high-frequency signal attenuation increases
Solution Approach 1:
The patent replaces the complex tri-plate structure with simple series-connected common mode choke coils that have minimal impact on high-frequency signal transmission. These choke coils provide the necessary delay time equalization without causing significant signal attenuation, effectively substituting a simpler component for a more complex one.
3Area of stationary object
If wire length is shortened to reduce wiring area, then wiring area decreases, but delay time equalization becomes difficult
Solution Approach 1:
The patent introduces common mode choke coils as intermediary components in the differential transmission lines. These choke coils act as mediators that add controlled delay times to shorter wires, enabling delay time equalization across wires of different lengths without requiring all wires to be the same physical length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the wiring area and maintains signal waveform quality in high-frequency regions by shortening the clock wire length using a common mode choke coil, which eliminates the need for damping resistors and reduces noise components, allowing for efficient data transfer without signal degradation.
Implementation Method 1
a plurality of equal-length wires which include a differential transmission line connected via a common mode choke coil
Data Source
AI summary
In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.