Memory Circuit Decoder Signal Buffering for Temperature Stability
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Solution Overview
Problem
Semiconductor memory circuits face functional issues at varying temperatures due to the variation in electrical characteristics of PMOS and NMOS transistors, leading to reduced nominal operating frequencies and performance degradation, especially at lower temperatures.
Innovation Solution
The memory circuit design incorporates an address control signal buffer that converts address signals into inverted signals, using NOR gates as the first stage for the second decoder to minimize signal degradation and maintain performance stability across a temperature range, while employing NAND gates for the first decoder to optimize cell selection signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory circuit uses conventional decoder design without temperature compensation, then the circuit structure remains simple, but the operating frequency decreases and performance degrades at lower temperatures
Solution Approach 1:
The patent applies different gate types (NAND vs NOR) to different decoders based on their specific requirements. The first decoder uses NAND gates optimized for its function, while the second decoder uses NOR gates optimized for its function, allowing each component to have locally optimized characteristics rather than a uniform design throughout the system.
Solution Approach 2:
The patent changes the operational parameters of the decoders by selecting different logic gate types (NAND/NOR) and configuring them with specific transistor arrangements. This parameter optimization allows the decoders to maintain stable performance across temperature variations while managing the complexity through targeted rather than comprehensive redesign.
2Productivity
If the memory circuit operates at higher frequencies, then productivity increases, but signal degradation and voltage drops increase due to temperature variations
Solution Approach 1:
The patent performs preliminary optimization of the decoder circuit design by selecting appropriate gate types and transistor configurations before operation. This preliminary action ensures that the circuit is pre-configured to compensate for temperature-induced signal degradation, allowing higher operating frequencies to be achieved without compromising signal stability during actual operation.
Solution Approach 2:
The patent uses complementary logic gate designs (NAND and NOR gates with corresponding transistor arrangements) in the two decoders. This copying approach with inverted logic ensures that signal degradation effects are balanced and compensated across the decoder stages, maintaining overall signal stability even at higher operating frequencies where such effects are magnified.
Data Source
AI summary
The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.