Asynchronous FIFO Control via Median Water Level
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Solution Overview
Problem
Existing systems lack specific mechanisms for coordinating asynchronous first-in first-out processes, leading to the need for large memory buffers to prevent overflow and underflow, which increases costs and complexity.
Innovation Solution
A control system that includes a data access circuit and a control circuit, which generates write and read indices based on different clocks, calculates water levels, and performs the asynchronous first-in first-out process at the median water level to synchronize data exchange between write and read circuits, allowing for efficient data transfer without requiring large memory buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large memory buffer is used to prevent overflow and underflow in asynchronous FIFO processes, then the reliability of data transfer is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a feedback mechanism by continuously monitoring the water level (difference between write index and read index) in the memory buffer and using this information to control the asynchronous FIFO operation. The control circuit adjusts the write enable and read enable signals based on the water level feedback, ensuring reliable data transfer while maintaining a compact buffer size.
Solution Approach 2:
The patent changes the operational parameters of the asynchronous FIFO by dynamically adjusting the write and read enable signals based on the water level. Instead of using a fixed large buffer, the system modifies its behavior parameters (enable signals) according to the current buffer occupancy state, achieving reliable transfer with reduced memory requirements.
2Reliability
If a large memory buffer is used to prevent overflow and underflow in asynchronous FIFO processes, then the reliability of data transfer is improved, but the manufacturing cost increases
Solution Approach 1:
The control circuit uses water level feedback to dynamically control the FIFO operation, replacing the need for oversized buffers. This feedback-based approach reduces the amount of physical memory required, directly lowering manufacturing costs while preserving data transfer reliability through intelligent control.
Solution Approach 2:
The system performs self-regulation by automatically adjusting its operation based on internal water level conditions. The control circuit monitors the buffer state and autonomously adjusts enable signals to prevent overflow and underflow, eliminating the need for external intervention or oversized buffers, thereby reducing manufacturing complexity and cost.
3Device complexity
If asynchronous FIFO processes are coordinated without specific mechanisms, then the device complexity is reduced, but the memory buffer size must be increased to prevent overflow and underflow
Solution Approach 1:
The patent introduces a feedback-based water level monitoring mechanism that tracks the difference between write and read indices. This feedback information is used by the control circuit to dynamically adjust operation, enabling efficient coordination with minimal buffer size. The feedback mechanism provides the necessary coordination intelligence without requiring complex external control structures.
Solution Approach 2:
The water level calculation acts as an intermediary that bridges the write and read operations. By computing and monitoring the water level (index difference), the system creates a simple mediation mechanism that coordinates asynchronous operations effectively, avoiding the need for complex direct coordination while minimizing buffer requirements.
Data Source
AI summary
A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.