Row Hammer Management Circuit for Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in defending against row hammer attacks, which can lead to data loss due to intensive access to specific memory cell rows, and existing solutions increase power consumption and overhead, especially as memory capacity increases.
Innovation Solution
A semiconductor memory device with a row hammer management circuit that counts access frequencies, stores candidate hammer addresses in a FIFO queue, and performs a hammer refresh operation on adjacent memory cell rows, using a refresh control circuit to mitigate row hammer effects while managing all memory cell rows effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing row hammer defense solutions are implemented, then data loss prevention is improved, but power consumption and overhead increase
Solution Approach 1:
The memory device performs self-diagnosis and self-protection against row hammer attacks. The row hammer management circuit autonomously monitors access patterns, identifies victim rows, and executes refresh operations without external intervention, reducing the burden on the memory controller and overall system power consumption.
Solution Approach 2:
The system proactively identifies potential victim rows before actual data corruption occurs by monitoring access patterns and detecting rows that are frequently accessed alongside aggressor rows. Refresh operations are performed in advance on these identified victim rows, preventing data loss rather than reacting after damage occurs.
2Reliability
If existing row hammer defense solutions are implemented, then data loss prevention is improved, but device complexity and overhead increase
Solution Approach 1:
The row hammer management circuit is designed to handle multiple functions within a single integrated structure: it monitors access patterns, identifies aggressor and victim rows, manages refresh operations, and interfaces with the memory controller. This multi-functional design reduces overall device complexity compared to having separate circuits for each function.
Solution Approach 2:
The patent combines the row hammer detection logic, victim row identification, and refresh control into a single integrated row hammer management circuit. This merging of functions reduces the number of separate components and interconnections, thereby reducing overhead and simplifying the overall device architecture.
3Quantity of substance
If memory capacity is increased, then storage capability is improved, but row hammer attack vulnerability and power consumption increase
Solution Approach 1:
The memory device is divided into multiple banks, each with its own row hammer management circuit. This segmentation allows independent monitoring and protection of each bank, enabling the system to scale to larger capacities while maintaining effective row hammer defense in each segment without requiring a proportional increase in overall protection complexity.
4Reliability
If comprehensive row hammer management is implemented, then data loss prevention is improved, but access speed and productivity may decrease
Solution Approach 1:
The row hammer management circuit performs refresh operations periodically on identified victim rows rather than continuously monitoring and refreshing all rows. This periodic action approach prevents data loss while minimizing interference with normal memory access operations, thereby maintaining higher access speeds and productivity.
Data Source
AI summary
A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.