SRAM Bit-Cell Read Buffer Transistor for Half-Select Data Flip
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Solution Overview
Problem
Conventional SRAM memory devices experience data flip issues during write operations due to row half-select problems, leading to increased power consumption and difficulty in miniaturization due to the need for write-back operations and a large number of transistors.
Innovation Solution
The proposed memory device incorporates a drive transistor unit, read buffer transistors, and block mask transistors to manage voltages during read and write operations, allowing for bit-interleaving without write-back operations, reducing unnecessary power consumption, and minimizing transistor count for smaller area and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit-interleaving structure is used to prevent soft errors, then reliability is improved, but row half-selected bit-cells experience data flip during write operations due to read disturbance
Solution Approach 1:
The patent introduces a read buffer transistor as an intermediary component between the bit line and the data storage node. This read buffer transistor selectively connects the bit line to the data storage node only when needed for read operations, preventing direct connection during write operations that would cause read disturbance in half-selected bit-cells. The read buffer acts as a mediator that controls the timing and path of signal flow to eliminate the harmful read disturbance effect.
2Reliability
If write-back operation is performed to correct data flip in row half-selected bit-cells, then reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies preliminary anti-action by using the read buffer transistor to prevent read disturbance before it can cause data flip in the first place. Instead of allowing the harmful effect to occur and then correcting it through write-back operations, the read buffer transistor proactively blocks the disturbance path during write operations. This preventive approach eliminates the need for power-consuming write-back operations while maintaining data integrity.
3Area of stationary object
If conventional SRAM structure with 8 transistors per bit-cell is used, then area is reduced, but data flip occurs in row half-selected bit-cells during write operation
Solution Approach 1:
The patent applies local quality by adding the read buffer transistor only at specific locations where it is most needed - at the intersection of bit lines and word lines where half-selected bit-cells are located. This localized addition provides targeted protection against read disturbance without requiring a complete restructuring of the entire bit-cell array, thus minimizing the increase in area while effectively preventing data flip in half-selected bit-cells.
4Reliability
If read buffer transistor is added to prevent read disturbance, then read stability is improved, but transistor count increases
Solution Approach 1:
The read buffer transistor is designed to perform multiple functions: it acts as a switch for read operations, prevents read disturbance during write operations, and selectively connects bit lines to data storage nodes. By making this single transistor multi-functional, the patent achieves improved read stability and prevention of data flip without requiring multiple separate components, thus limiting the increase in device complexity.
Data Source
AI summary
Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.