SRAM Control Circuitry for Parallel Column Access
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Solution Overview
Problem
The speed of processing units is limited by the latency in read and write operations to and from memory, particularly in static random access memory (SRAM), which can be improved by reducing the number of clock cycles required for accessing multiple bitcells.
Innovation Solution
Implementing control circuitry with a state machine, registers, and a column selection control circuit to enable 'blast mode' operations, allowing simultaneous access to multiple columns in SRAM, including a wordline driver and input/output circuitry to manage these operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential access method is used for multiple bitcells, then memory access is simple and reliable, but the number of clock cycles increases and throughput decreases
Solution Approach 1:
The memory array is segmented into multiple independently accessible columns (e.g., column 0, column 1, column 2, column 3). Each column can be accessed simultaneously through parallel column selection circuits, allowing multiple bitcells to be read or written in the same clock cycle. This segmentation transforms sequential access into parallel access, directly reducing the number of clock cycles required for multi-bitcell operations.
Solution Approach 2:
Multiple column access operations are merged into a single clock cycle by combining column selection signals and enabling simultaneous activation of multiple column decoders. The control circuitry merges the timing and coordination of multiple column operations, allowing what would traditionally require multiple sequential cycles to be completed in parallel within one cycle.
2Productivity
If simultaneous access to multiple columns is implemented, then throughput increases, but control circuitry complexity increases
Solution Approach 1:
Column addresses and selection signals are prepared and staged in advance in register files before being latched and activated. The control circuitry performs preliminary setup of column selection states, so that when simultaneous column access is required, the signals are already ready and coordinated. This preliminary action reduces the real-time control complexity during the actual parallel access operation.
Solution Approach 2:
Register files and control registers act as intermediary elements between the control logic and the column decoders. These intermediaries buffer and coordinate the control signals, simplifying the overall control architecture by decoupling the complexity of simultaneous column selection from the column decoder logic itself. The intermediary structures manage the timing and coordination, making the control circuitry more modular and manageable.
Data Source
AI summary
Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a column selection control circuit that combines outputs of the state machine and the set of registers to trigger an appropriate column during an appropriate clock cycle, available at a start of a corresponding clock cycle. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.