Asymmetric Semiconductor Memory Cell Array Design
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Solution Overview
Problem
In miniaturized semiconductor memory devices, the half-select bias system leads to voltage drop inconsistencies and mixing of half-selected cell currents with selected cell currents, making it difficult to maintain constant voltage and accurate data read during reduction scaling.
Innovation Solution
A semiconductor memory device configuration with a memory cell array intersecting row and column lines, where the ratio of cell currents is managed by a decoder, ensuring M^2 < 2*N*k, and asymmetrical array sizing with biased voltages to maintain constant voltage drops and signal ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell size is reduced through miniaturization, then integration density is improved, but voltage drop becomes inconsistent and difficult to control
Solution Approach 1:
The patent applies asymmetry by configuring the memory cell array with different numbers of row lines and column lines (M rows and N columns where M≠N), specifically designing an asymmetrical cross-point structure where the selected cell current path has fewer intersections than the unselected cell current paths. This asymmetrical configuration ensures that the selected cell current is not contaminated by half-selected cell currents, maintaining consistent voltage drops even as cell size is reduced for higher integration density.
2Ease of operation
If half-select bias system is used, then selection capability is improved, but half-selected cell current mixes with selected cell current making read difficult
Solution Approach 1:
The patent uses an asymmetrical cross-point memory cell configuration where the selected cell current path contains fewer cell intersections compared to unselected cell current paths. This asymmetry creates a natural filtering effect where half-selected cell currents do not form complete current paths, thereby preventing contamination of the selected cell current signal and enabling accurate read operations while maintaining selection capability.
Solution Approach 2:
The patent applies local quality by creating different current path characteristics at different locations within the memory cell array. The selected cell current path is specifically designed to have minimal intersections, while unselected paths inherently have more intersections that block half-selected currents. This localized optimization of current path quality enables precise signal discrimination between selected and unselected cells.
3Quantity of substance
If cell size is reduced, then integration is improved, but proportion of mixed-in half-selected cell current increases
Solution Approach 1:
The patent employs asymmetrical configuration of the memory cell array with M row lines and N column lines where the selected cell accesses a unique path with minimal intersections. This asymmetrical design ensures that as cell size is reduced and integration density increased, the proportion of half-selected cell current contamination remains suppressed because the asymmetrical structure inherently blocks incomplete current paths regardless of scaling.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.