Three-Port SRAM Circuit Synchronous Multi-Port Read
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Solution Overview
Problem
Existing SRAM circuits are limited in their ability to operate multiple ports simultaneously at high speeds, which hinders system performance in multi-port access scenarios.
Innovation Solution
A three-port SRAM circuit design that incorporates additional transistors and bit lines, allowing for synchronous operation of port B and port C during read operations without the need for an inverter to determine storage states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-port SRAM circuit is used, then the circuit structure is simple, but the system cannot operate multiple ports simultaneously at high speeds
Solution Approach 1:
The SRAM circuit is segmented into three independent ports (Port A, Port B, Port C), each with dedicated bit lines and word lines. Port A uses bit lines BL1/BL2, Port B uses bit line B-BL with transistors N5/N6, and Port C uses bit line C-BL with transistors P3/P4. This segmentation allows simultaneous read operations on multiple ports without interference, resolving the contradiction between multi-port productivity and circuit complexity by organizing the circuit into modular, independent access paths.
Solution Approach 2:
The SRAM circuit achieves multi-functionality by enabling three different port configurations to access the same storage nodes (n1, n2) simultaneously. Port A provides full read/write capability, while Ports B and C provide high-speed read capability through shared bit lines. The circuit universally handles multiple access patterns through a unified transistor network, allowing the system to achieve high-speed simultaneous reads without requiring separate memory banks.
2Productivity
If additional transistors and bit lines are added for multi-port operation, then simultaneous read capability is improved, but the circuit complexity increases
Solution Approach 1:
The circuit merges Port B and Port C access paths with the existing Port A storage nodes. Transistors N5/N6 for Port B and P3/P4 for Port C are integrated into the same node structure as Port A, sharing the storage nodes n1 and n2. This merging approach enables simultaneous reads from all three ports while minimizing the increase in circuit complexity by reusing existing circuit elements rather than creating entirely separate access paths.
3Measurement precision
If an inverter is used to determine storage states in conventional SRAM, then the storage state can be determined, but the peripheral circuit operation speed is reduced due to logic overhead
Solution Approach 1:
The invention extracts and eliminates the inverter logic from the high-speed read path. By directly connecting the storage nodes n1 and n2 to the bit lines through transistors N5/N6 and P3/P4, the circuit determines storage states without requiring inverter-based logic. This extraction of the inverter element from the critical path enables high-speed peripheral circuit operation while maintaining accurate storage state determination through direct voltage level detection on the bit lines.
Data Source
AI summary
The present application discloses a three-port SRAM circuit, which is formed by adding two read ports to a six-transistor single-port SRAM circuit. Storage states of a first node and a second node of the six-transistor single-port SRAM circuit are opposite, so that a third P-type transistor with a gate terminal thereof corresponding to the first node and a fifth N-type transistor with a gate terminal thereof corresponding to the second node can be on/off synchronously. When a sixth N-type transistor and a fourth P-type transistor are both on, a port C bit line and a port B bit line can be held/discharge synchronously, so as to facilitate a system operating a peripheral circuit simultaneously when reading ports B and C at high speeds.