Row Decoder Circuit for Phase Change Memory
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Solution Overview
Problem
The existing row decoder architecture for phase change non-volatile memory devices is complex and occupies a large area due to its hierarchical decoding levels and distinct paths for reading and programming operations, which complicates integration and increases area occupation.
Innovation Solution
A row decoder circuit with a global predecoding stage that generates high-voltage decoded address signals and a selection driving unit to produce block-address signals, along with a row-driving unit using medium-voltage transistors to bias wordlines, simplifying the architecture and reducing area occupation while maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical decoding levels and distinct paths for reading and programming operations are used, then selection and biasing of rows can be achieved, but device complexity and area occupation increase
Solution Approach 1:
The patent merges the reading path and programming path into a single unified decoder architecture. Instead of maintaining separate hierarchical decoding levels and distinct signal paths for reading and programming operations, the invention combines these functions into one integrated decoder that handles both operations through a common structure, thereby reducing device complexity and area occupation while maintaining full functionality
2Reliability
If multiple supply voltages are used for reading and programming operations, then electrical performance can be optimized, but device complexity increases
Solution Approach 1:
The patent implements a universal decoder circuit that can operate with multiple supply voltages (first supply voltage for reading, second supply voltage for programming) without requiring separate dedicated circuits for each operation. The same decoder structure handles both reading and programming by accepting different voltage inputs, thereby optimizing electrical performance while avoiding the complexity of separate specialized circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution simplifies the row decoder architecture, reduces area occupation, and maintains access times and operational efficiency for reading and writing operations, making non-volatile PCM devices more competitive in terms of performance and cost.
Implementation Method 1
This electric current, by the Joule effect, generates the temperatures for a phase change
Implementation Method 2
Access devices (for example metal oxide field effect transistors (MOSFETs)), are connected to the heaters and enable selective flow of an electric programming current through a respective heater. This electric current, by the Joule effect, generates the temperatures for a phase change
Implementation Method 3
These materials may switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase. Resistivities with considerably different values, and consequently, a different value of a data stored are associated with the two phases
Data Source
AI summary
A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.