3T4M STT-MRAM Circuit Structure for High-Speed Low-Area Memory
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Solution Overview
Problem
Current spin transfer torque (STT) MRAM technologies with 1T2M or 2T2M dual-bits architecture suffer from slow reading and writing speeds, and face challenges in accommodating more memory cells in limited layout areas.
Innovation Solution
The proposed solution is a 3T4M STT-MRAM circuit structure with a dual-bits architecture, where each unit cell consists of three transistors and four magnetic tunnel junctions (MTJs), connected in a specific configuration to enhance reading and writing speeds and reduce layout area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1T2M or 2T2M dual-bits architecture is adopted, then device complexity is reduced, but reading speed and writing speed become slow
Solution Approach 1:
The patent segments the memory unit cell into multiple independent transistor-MTJ pathways (three transistors T1-T3 and four MTJs MTJ1-MTJ4 arranged in parallel branches). This segmentation allows simultaneous activation of multiple current paths during read/write operations, enabling parallel processing of data bits and thereby increasing operating speed while maintaining manageable device complexity through modular architecture.
2Ease of manufacture
If 1T2M or 2T2M dual-bits architecture is adopted, then manufacturing simplicity is improved, but layout area efficiency deteriorates
Solution Approach 1:
The patent merges multiple MTJs (four MTJs in total) and transistors (three transistors) into a compact unit cell structure where components are shared and interconnected efficiently. The parallel arrangement of transistor-MTJ branches allows better space utilization compared to sequential arrangements, reducing the layout area per memory cell while maintaining manufacturing simplicity through standardized component integration.
3Quantity of substance
If more memory cells are accommodated in limited layout area, then storage density is improved, but signal interference and cross-talk increase
Solution Approach 1:
The patent introduces carefully designed isolation structures and shielding elements as intermediaries between adjacent memory cells and circuit components. These intermediary elements act as barriers that block or attenuate electromagnetic interference and cross-talk signals, enabling higher memory cell density to be achieved without significant degradation in signal integrity or increased interference levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3T4M STT-MRAM circuit structure significantly improves reading and writing speeds and reduces the necessary layout areas, enabling more efficient data storage and retrieval while maintaining low power consumption.
Implementation Method 1
an MRAM cell stores data by applying external magnetic fields to control the magnetic polarity and tunneling magnetoresistance (TMR) of the magnetic tunnel junction
Implementation Method 2
the mechanism of spin transfer torque (STT) MRAM is to flip the magnetization direction through the torque generated by the electron spin energy applied on the ferromagnetic atoms
Data Source
AI summary
A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.