SRAM Shmoo Plot Construction via Independent Voltage Control
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Solution Overview
Problem
In integrated circuits with SRAM arrays, existing testing methods cannot independently control wordline, array, and bitline voltages during operational feature tests, making it difficult to determine the type of failure (read, write, or stability) when SRAM bits fail at measurement points, limiting the ability to diagnose and improve specific operational features.
Innovation Solution
The implementation of a built-in self-test circuit block with independent control of wordline, array, and bitline voltages allows for the determination of the type of operational feature failure during testing, using test circuitry to extend pulse widths, adjust delays, and drive bitlines, enabling the creation of detailed Shmoo plots that specify both the number and type of failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used, then testing can be performed with simple circuitry, but the type of operational feature failure cannot be determined
Solution Approach 1:
The test circuitry is segmented into separate control units for independently controlling wordline voltage, array voltage, and bitline voltage. This segmentation allows each voltage parameter to be controlled and varied independently, enabling the identification of which specific operational feature (read, write, or stability) fails at different voltage conditions, thereby improving failure type identification without requiring complete redesign of the entire test system
Solution Approach 2:
A built-in self-test circuit block is introduced as an intermediary between the SRAM array and the testing system. This intermediary circuitry includes voltage control units that mediate the application of test voltages to the SRAM array, allowing precise control and measurement of voltage conditions during testing, which enables detailed failure mode analysis without requiring external complex testing equipment
2Adaptability or versatility
If independent voltage control is implemented, then operational feature failure types can be identified, but the test circuitry complexity increases
Solution Approach 1:
The built-in self-test circuit block is designed with multi-functionality, serving as a universal test platform that can perform read tests, write tests, and stability tests by simply varying the voltage control parameters. The same circuitry can independently control wordline, array, and bitline voltages across different test modes, eliminating the need for separate dedicated circuitry for each test type and reducing overall complexity despite the enhanced versatility
Solution Approach 2:
The test circuitry incorporates dynamic voltage control capabilities where the voltage levels for wordline, array, and bitline can be dynamically adjusted during testing. This dynamic control allows the system to adapt to different test conditions and identify failure modes at various voltage points, providing flexibility without requiring multiple static circuit configurations
3Loss of information
If comprehensive operational feature testing is performed, then detailed failure information is obtained, but the testing time increases
Solution Approach 1:
The testing method performs preliminary actions by first conducting a comprehensive sweep through multiple voltage points for wordline, array, and bitline voltages to map out the failure boundaries. This preliminary voltage mapping establishes the test space boundaries and identifies regions of interest, allowing subsequent detailed failure analysis to be focused only on critical areas, thereby reducing overall testing time while maintaining comprehensive failure diagnosis capability
Solution Approach 2:
The testing approach uses periodic action by systematically cycling through different voltage combinations in a structured sequence. The test method periodically varies wordline voltage, array voltage, and bitline voltage through defined ranges, allowing efficient coverage of the entire test space. This periodic voltage variation pattern enables comprehensive failure mode identification without requiring exhaustive testing of every possible condition, optimizing the balance between information gain and testing time
Data Source
AI summary
A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.