2T0C Memory Cell Layout for Higher Density and Better Yield
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Solution Overview
Problem
The low yield of semiconductor structures due to capacitor collapse during manufacturing, particularly as the aspect ratio of the capacitor increases, and the reduced storage density caused by large memory cells containing both a capacitor and a transistor.
Innovation Solution
A semiconductor structure and manufacturing method where first and second transistors are electrically connected and extend parallel to the substrate, forming a 2T0C structure, reducing the area occupied by memory cells and improving storage density by eliminating the need for a capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of the capacitor is increased to improve storage capacity, then the storage capacity is improved, but the manufacturing difficulty increases and yield decreases due to capacitor collapse
Solution Approach 1:
The patent transitions from traditional vertical capacitor structures to a horizontal transistor arrangement where two transistors are connected in parallel along the first direction. This dimensional change eliminates the need for high aspect ratio capacitors while maintaining storage functionality, thereby resolving the contradiction between storage capacity and manufacturing yield.
Solution Approach 2:
Instead of increasing capacitor height to improve storage capacity, the patent inverts the approach by using two transistors connected in parallel at the same level. This inversion of the traditional vertical stacking approach allows improved storage capacity without the manufacturing difficulties associated with high aspect ratio capacitors.
2Quantity of substance
If the memory cell size is reduced to improve storage density, then the storage density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges two transistors into a single transistor unit structure where they share common components and are connected in parallel. This merging approach reduces the overall memory cell area and simplifies the structure while improving storage density, counteracting the expected increase in complexity.
Solution Approach 2:
The transistor unit is designed with multi-functionality where two transistors share common bit lines and word lines, and can operate independently or together. This universal design allows the same structural unit to serve multiple functions, reducing the need for additional specialized components and simplifying the overall memory cell structure.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.