2T1C Vertical 3D Memory Cell for Retention and Leakage Control
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Solution Overview
Problem
Existing memory technologies face challenges in achieving good retention and scalability, particularly in vertical three-dimensional (3D) memory devices, with one transistor, one capacitor (1T1C) cells having limitations in signal margin and current leakage.
Innovation Solution
A two transistor, one capacitor (2T1C) cell design is introduced, where horizontally oriented transistors share a storage node, integrated with vertically oriented gates and horizontally oriented digit lines, improving retention and scalability by reducing horizontal area and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1T1C cell design is used, then device complexity is reduced, but retention and signal margin deteriorate
Solution Approach 1:
Two access transistors are merged to share a common storage node capacitor, creating a 2T1C configuration. This merging allows both transistors to control access to the same capacitor, improving signal margin and retention while maintaining reasonable device complexity through shared components.
Solution Approach 2:
The shared storage node capacitor serves multiple functions: it stores data for both access transistors, provides a common reference for differential signaling, and enables improved signal margin through differential read operations. This multi-functionality resolves the contradiction by achieving better reliability without proportionally increasing complexity.
2Quantity of substance
If vertical 3D memory is implemented, then density is improved, but current leakage increases
Solution Approach 1:
The memory structure is segmented into multiple tiers with horizontally oriented transistors and vertically oriented gates. This segmentation allows for better control of current paths, reducing leakage while maintaining high vertical density. The horizontal transistor orientation in each tier creates distinct current confinement zones.
Solution Approach 2:
The patent transitions from traditional planar transistor orientation to vertically oriented gates with horizontally oriented transistors in a 3D stacked architecture. This dimensional change enables high density through vertical stacking while the horizontal transistor orientation provides better current confinement, reducing leakage through the vertical structure.
3Area of stationary object
If horizontal area is reduced for scalability, then manufacturing precision requirements increase
Solution Approach 1:
The patent reduces horizontal footprint by transitioning to a vertical 3D architecture where memory cells are stacked in multiple tiers. Each tier contains horizontally oriented transistors with vertically oriented gates, allowing high density without requiring proportionally smaller feature sizes, thus managing manufacturing precision requirements.
Solution Approach 2:
Multiple memory cells across different tiers share common bit lines and word lines, reducing the total horizontal area required. This merging of interconnect resources allows scalability without proportionally reducing feature dimensions, maintaining feasible manufacturing precision requirements.
Data Source
AI summary
Systems, methods and apparatus are provided for a two access device, one storage node memory cell in a vertical three-dimensional memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. The memory cell has a second horizontally oriented access device having a first source/drain region and a second source/drain region separated by a second channel region. The second access device is operatively controlled by a second gate. A shared storage node is coupled between the second source/drain regions of the first access device and the second access device.