Digital Storage TRIZ Cases
- Antiferromagnetically Coupled Magnetic Track for Low-Current Domain Motion
Antiferromagnetically coupled magnetic layers and a spacer improve domain motion and tunnel magnetoresistance while lowering write current.
- MTJ Memory Cell Shield Layout Against External Magnetic Fields
A recessed magnetic shield layer between MTJ storage patterns blocks external field interference while avoiding extra patterning steps.
- Ferroelectric Tunnel Barrier Structure for Conductive Protrusion Control
Oxygen vacancies and a low-carrier metal oxide electrode help control conductive protrusions, improving on-off ratio and storage reliability.
- 3D Stacked Memory Layer Structure for Higher DRAM Density
Vertical transistor active layers enable stacked memory layers that raise DRAM density without the cost and difficulty of extreme transistor scaling.
- Low-k MTJ Spacer Structure for High-Frequency MRAM
Low-k oxide and nitride spacers around the MTJ cut capacitance between adjacent MRAM cells, reducing RC delay for high-frequency operation.
- Magnetic Memory Structure for Low-Current Magnetization Switching
An opposite-side magnetic layer uses spin-orbit torque to switch free-layer magnetization at lower critical current and power.
- Spin-Orbit Torque MRAM Switching to Lower Write Current
Sidewall spin-orbit torque assists spin-transfer switching in magnetic tunnel junctions, cutting write current and breakdown risk.
- Heusler MRAM Layer Stack for Lower STT Switching Current
Alternating Co-E layers and an insertion layer tune Heusler PMA, lowering coercivity and anisotropy for STT switching in thicker MRAM cells.
- Stacked SOT-MRAM Architecture With Shared SHE Rail
A shared low-resistivity SHE rail links stacked vertical MRAM cells to raise density while limiting write-line resistance and back sputtering.
- Magnetic Tunnel Junction Layer Structure for Stable TMR and Exchange Field
An amorphous CoFeBX buffer and W, Mo, or Ta auxiliary layer block diffusion and crystalline collisions to preserve TMR and exchange field.
- Series MTJ p-Bit Circuit for Wider Stochastic Tunability
Multiple MTJs in series with a source resistor and comparator broaden p-bit stochastic range and enable smoother probability tuning.
- Decoupled p-Bit Generator Circuit for Tunable Probabilistic Computing
A decoupled stochastic and control path uses sMTJ voltage-divider p-bits to improve tunability, reduce errors, and scale probabilistic computing.
- MTJ Switching With a Chiral PSM Layer for Lower Current
A chiral PSM layer beside the MTJ free layer adds spin-transfer torque, lowering switching current without thickening the stack.
- SAF Magnetic Tunnel Junction Structure for Lower Field Interference
A simplified SAF fixed-layer stack cancels stray magnetic fields, improves data retention, and reduces surface roughness in MRAM cells.
- MRAM Top Electrode Composition for TMR Speed and Retention
Different N/Ti ratios and spacer thicknesses tune MTJ TMR across MRAM array regions to improve speed, retention, power use, and cost.
- Dynamic Memory Bank Interleaving for Higher Access Throughput
Interleaving commands across memory bank groups cuts idle access gaps and raises dynamic memory throughput for real-time ADAS and AV workloads.
- Dual MTJ Stack With SOT/STT Switching for Two-Bit MRAM
A dual magnetic tunnel junction stack uses a shoulder electrode for independent SOT and STT switching, enabling two-bit storage with lower power dissipation.
- MTJ Interconnect Structure for Compact, Low-Power MRAM Sensing
Metal interconnect protrusions contacting MTJ-side liners improve alignment, cut chip area and power use, and reduce temperature sensitivity.
- SRAM Cell Layout With Selective PG Fin Narrowing
Dummy fins selectively narrow PG fins while keeping PD fins wider, improving SRAM beta ratio and static noise margin.
- Semiconductor Life Prediction Using dV/dt Recording
Recording the peak dV/dt at an electrode enables on-chip life and degradation prediction with less added monitoring complexity.
- MTJ Seed Layer Structure for Heat-Stable Pinned Layer Crystallinity
A Re/Ru multilayer seed layer helps magnetic tunnel junctions preserve pinned-layer crystal quality, RA, and TMR after heat treatment.
- Rhenium Seed Layers in MTJs for High-Temperature Anneal Stability
A rhenium or Re/Ru seed layer helps magnetic tunnel junctions preserve TMR and magnetic properties after high-temperature annealing.
- High-Voltage Isolation Layout for 3D NAND Leakage Control
Narrow and interdigitated active areas isolate 3D NAND erase voltages from low-voltage circuits while cutting leakage and layout area.