Ferroelectric Memory Cell Structure for Reliable Program and Erase
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Solution Overview
Problem
Conventional n-type ferroelectric field-effect transistors (FeFETs) face challenges in programming and erasing operations due to the interaction of different charge carriers, particularly when dealing with p-body or un-doped bodies, which affects the performance and reliability of the memory cell array structure.
Innovation Solution
The implementation of ferroelectric tunneling field-effect transistors (FeTFETs) with source and drain regions doped with different conductivity types (n-type and p-type dopants) enhances control over charge carrier movement, eliminating the need for channel doping and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional n-type FeFETs are used with p-body or un-doped bodies, then the device structure is simpler, but programming and erasing operations become unreliable due to charge carrier interaction
Solution Approach 1:
The patent applies local quality by doping the source and drain regions with different dopant types (n-type and p-type) while keeping the channel lightly-doped or undoped. This creates asymmetric local properties that enable reliable charge carrier control during programming and erasing operations without requiring a complex p-body structure throughout the entire device.
Solution Approach 2:
The patent changes the doping parameters of the source and drain regions, specifically using different dopant types and concentrations. The first doped region uses n-type dopant with concentration between 1E18-1E20 atoms/cm³, while the second doped region uses p-type dopant with similar concentration range, enabling reliable operation without complex device structure.
2Reliability
If channel doping is performed to improve transistor performance, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the heavy doping requirement from the channel region and relocates it to the source and drain regions only. The channel is kept lightly-doped or undoped with concentration less than 1E16 atoms/cm³, simplifying the manufacturing process while maintaining transistor performance through the asymmetrically doped source and drain regions.
3Ease of manufacture
If source and drain regions are doped with same conductivity type, then manufacturing process is simpler, but control over charge carrier movement is reduced
Solution Approach 1:
The patent implements local quality by assigning different doping types to different regions: the first doped region (source) uses n-type dopant while the second doped region (drain) uses p-type dopant. This asymmetric local doping configuration enables precise control over charge carrier movement during programming and erasing operations, with each region contributing different charge carriers as needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the overall functionality of the FeTFETs on the memory cell array structure by enabling efficient programming and erasing operations, reducing manufacturing complexities, and enhancing device reliability.
Implementation Method 1
The first ferroelectric layer is over the channel layer and between the first and second doped regions
Implementation Method 2
a memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer
Data Source
AI summary
The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.