SRAM Fin Layout With Differential Width Control for Beta Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SRAM technologies face challenges in improving the beta ratio and static noise tolerance due to limitations in controlling the width of fin structures formed by spacer imaging transferring (SIT).
Innovation Solution
The method involves adding dummy fin structures and forming a mandrel pattern with a special shape to control the width of fin structures. More dummy fins are placed around the PG fin structure, while none are around the PD fin structure, allowing for differential etching to reduce the PG fin width and maintain the PD fin width, thereby enhancing the beta ratio and static noise tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of fin structure is increased to improve beta ratio, then the turn-on current of PD transistor increases, but the width cannot be adjusted freely due to SIT process limitations
Solution Approach 1:
The patent applies local quality by creating different fin structure widths for different transistor types within the same SRAM cell. Specifically, PD transistors are given wider fin structures while PG transistors have narrower fin structures, allowing each transistor type to have optimized electrical characteristics tailored to its specific function in the circuit.
Solution Approach 2:
The patent changes the physical parameter of fin structure width to control transistor characteristics. By adjusting the width of fin structures through dummy fin addition and selective etching, the patent modifies the turn-on current of transistors to achieve the desired beta ratio improvement without changing other process parameters.
2Reliability
If dummy fin structures are added around PG fin structure to reduce its width via reflection etching, then the beta ratio improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies preliminary action by adding dummy fin structures before the final etching process. These dummy fins are strategically positioned around the PG fin structure to create reflection etching effects during subsequent processing steps, which automatically reduces the PG fin width to the desired dimension without requiring additional precise patterning steps.
Solution Approach 2:
The dummy fin structures serve as intermediary elements that mediate between the patterning process and the final fin structure dimensions. By introducing these intermediate structures, the patent enables indirect control of PG fin width through reflection etching, avoiding the need for direct precise patterning of the PG fins themselves.
3Reliability
If the width of PG fin structure is reduced to increase beta ratio, then static noise tolerance improves, but the control precision over fin width is limited by conventional methods
Solution Approach 1:
The patent applies local quality by creating different fin structure widths for different transistor types within the same SRAM cell. Specifically, PD transistors are given wider fin structures while PG transistors have narrower fin structures, allowing each transistor type to have optimized electrical characteristics tailored to its specific function in the circuit.
Solution Approach 2:
The patent utilizes the hydraulic analogy of etching fluid dynamics, where reflection etching creates localized variations in etch rate based on proximity to dummy fin structures. This approach enables precise local control of fin width by manipulating the etching environment rather than relying solely on mechanical patterning precision.
Data Source
AI summary
The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.