Bytewide Write-Enable Memory Compression for Better Array Utilization
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Solution Overview
Problem
Current techniques for converting user-designed memory into hardware implementations often result in poor memory utilization due to mismatches between the dimensions of the user-designed memory and the aspect ratios of physical memory elements, leading to underutilization of memory elements.
Innovation Solution
A method that involves designing a core memory array, identifying groups of nodes for compression into physical memory elements, and generating input and output circuitry using a data replicator and write enable generator to efficiently map and write data into physical memory elements, allowing for increased memory utilization by compressing multiple nodes into a single element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If user-designed memory dimensions are directly mapped to physical memory elements, then implementation is simple, but memory utilization is poor
Solution Approach 1:
The physical memory element is segmented into multiple virtual nodes through the compression architecture. Each physical memory element is divided into N segments, where each segment corresponds to a virtual node in the user-defined memory. This segmentation allows a single physical element to serve multiple logical memory locations, improving utilization while maintaining simple mapping through address decoding.
Solution Approach 2:
Multiple virtual memory nodes are nested within a single physical memory element. The compression logic nests N virtual node addresses within one physical element's address space, allowing the physical element to contain multiple logical memory locations. This nesting achieves high memory utilization without complex external mapping.
2Quantity of substance
If multiple nodes are compressed into a single physical memory element, then memory utilization is improved, but write operation complexity increases
Solution Approach 1:
The write enable signal is applied partially to only the selected node within the compressed group rather than to all nodes. The compression logic activates the write enable for exactly one node at a time based on the address, performing partial action on the replicated data. This avoids the complexity of selective writing to multiple nodes while maintaining simple write circuitry.
Solution Approach 2:
Compression logic acts as an intermediary between the write interface and the physical memory element. This intermediary receives the write enable signal and address, determines which node is selected, and conditionally enables writing to only that specific node. The intermediary simplifies the overall system by handling the complexity internally while presenting a simple write interface externally.
3Productivity
If data is replicated before transmission to physical memory elements, then compression efficiency is improved, but input circuitry complexity increases
Solution Approach 1:
The data replication function is merged with the compression logic in a single integrated circuit block. Rather than having separate replication and compression circuits, the design combines these functions into one unit that simultaneously replicates data to multiple virtual nodes and compresses them into the physical memory element. This merging reduces overall input circuitry complexity while maintaining high compression efficiency.
Data Source
AI summary
Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.