Column Address Latch Timing for Multi-Bank Semiconductor Memory
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently performing column operations across multiple bank groups due to synchronization issues and pulse width degradation, particularly in modes like 8-bank and 16-bank operations, where burst lengths and bubble periods complicate simultaneous data retrieval from multiple banks.
Innovation Solution
The semiconductor device incorporates a column delay circuit and an internal column delay circuit to generate delayed control pulses, which are used by an address latch circuit and column address generation circuit to synchronize and buffer addresses, ensuring stable column operations across multiple banks by controlling pulse widths and logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column operations are performed across multiple bank groups simultaneously, then data retrieval efficiency is improved, but synchronization issues and pulse width degradation occur
Solution Approach 1:
The patent divides the column control pulse generation into separate segments: a column delay circuit generates delayed column control pulses for first bank groups, while an internal column delay circuit generates delayed internal column control pulses for second bank groups. This segmentation allows independent timing control for different bank groups, resolving synchronization issues when performing column operations across multiple bank groups simultaneously.
2Productivity
If burst length is increased for faster data retrieval, then productivity is improved, but pulse width degradation and synchronization issues worsen
Solution Approach 1:
The patent applies preliminary action by generating delayed column control pulses and delayed internal column control pulses in advance through the column delay circuit and internal column delay circuit, respectively. These pre-delayed pulses are prepared before simultaneous column operations on multiple bank groups, ensuring that even with increased burst lengths, the pulse widths remain properly controlled and synchronized without degradation.
3Productivity
If column operations are performed on multiple banks simultaneously, then data retrieval efficiency is improved, but address synchronization becomes more difficult
Solution Approach 1:
The patent introduces intermediary elements in the form of the column delay circuit and internal column delay circuit, which act as mediators between the address latch circuit and the simultaneous column operations on multiple bank groups. These delay circuits buffer and synchronize the control pulses, simplifying the address synchronization process even when performing column operations on multiple banks simultaneously.
Data Source
AI summary
A semiconductor device includes an address latch circuit and a column address generation circuit. The address latch circuit latches an address based on an input control signal generated according to a column control pulse and outputs the latched address as a pre-column address based on an output control signal generated according to an internal column control pulse. The column address generation circuit generates a column address from the pre-column address based on a delayed column control pulse and a delayed internal column control pulse.