Folded Register Latency Shifter Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional latency shifters in memory devices face issues with large gate and wiring capacitances, leading to undesirably high charge/discharge currents and speed differences due to varying numbers of selectors and flip-flops, which affect signal delay and propagation efficiency.
Innovation Solution
A latency shifter design with a folded layout of registers and multiplexers, where input and output registers are adjacent, allowing for efficient signal propagation with reduced parasitic capacitance and optimized clock distribution, enabling high-speed operation by aligning fan-outs and minimizing critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional latency shifter designs use multiple lines of flip-flops with different lengths, then signal delay flexibility is improved, but gate and wiring capacitances increase leading to higher charge/discharge currents
Solution Approach 1:
The patent merges multiple flip-flop lines into a single folded topology where flip-flops are arranged in a linear sequence that folds back on itself. This consolidation reduces the number of separate signal paths and selectors, thereby reducing total gate and wiring capacitance while maintaining the ability to achieve different delay values by selecting different numbers of flip-flops in the folded chain.
Solution Approach 2:
The patent transforms the conventional two-dimensional layout with multiple parallel lines into a one-dimensional folded sequence. By arranging flip-flops in a linear folded topology rather than parallel branches, the design reduces spatial separation between input and output, minimizing wiring length and parasitic capacitance while preserving delay flexibility through selective activation of different numbers of flip-flops.
2Adaptability or versatility
If conventional latency shifters route signals through varying numbers of selectors, then delay adjustment is improved, but speed differences occur due to varying signal paths
Solution Approach 1:
The patent applies local quality by ensuring that each flip-flop in the folded topology has identical electrical characteristics and loading conditions. By arranging flip-flops in a uniform folded sequence rather than varying parallel paths, each stage experiences the same local electrical environment, ensuring consistent propagation delay per stage regardless of the total number of flip-flops in the active path.
3Loss of time
If conventional designs place input and output flip-flops at opposite ends of a line, then maximum delay is achieved, but wiring length and parasitic capacitance increase
Solution Approach 1:
The patent transforms the linear arrangement into a folded configuration where the signal path folds back on itself, bringing the output flip-flop adjacent to the input flip-flop in physical space. This dimensional transformation allows the signal to traverse a long logical path through multiple flip-flops while maintaining short physical wiring length, as the folded topology wraps the long delay path into a compact spatial arrangement.
Data Source
AI summary
Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.