Semiconductor Memory Segmented Master Data Line Coupling
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Solution Overview
Problem
Traditional semiconductor memory devices require extensive routing and circuit area for data access and storage, leading to increased manufacturing costs.
Innovation Solution
The semiconductor memory design incorporates a plurality of sense amplifiers, master data line segments, and memory segments arranged in a column direction, with adjacent master data line segments coupled together to reduce wiring and circuit area, utilizing a global data bus and memory banks for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional memory routing is used to access and store mass data, then data access functionality is achieved, but routing complexity and circuit area increase
Solution Approach 1:
The memory device is divided into multiple memory banks, each containing multiple memory segments with their own sense amplifiers. Master data lines are segmented and coupled between adjacent segments, creating a hierarchical structure that reduces overall routing complexity while maintaining data access functionality across the entire memory array.
Solution Approach 2:
Memory segments are arranged in a two-dimensional array structure with row and column organization. The master data lines extend in the column direction, allowing data access to occur along multiple spatial dimensions rather than requiring complex planar routing, thereby reducing circuit area while preserving access capabilities.
2Device complexity
If traditional memory routing is used to access and store mass data, then data access functionality is achieved, but circuit area increases
Solution Approach 1:
Adjacent memory segments share common master data lines that are coupled together, eliminating the need for separate dedicated routing for each segment. This merging of routing resources reduces the total circuit area required while maintaining full data access functionality across all memory segments through the shared line structure.
Solution Approach 2:
The master data lines serve multiple functions: they act as data output lines from memory segments to sense amplifiers, as data input lines from sense amplifiers to memory segments, and as interconnects between adjacent segments. This multi-functionality reduces the number of dedicated routing lines needed, thereby reducing circuit area while preserving complete data access capability.
Data Source
AI summary
Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together.