SRAM Cell Layout With Selective PG Fin Narrowing
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Solution Overview
Problem
Existing SRAM technologies face challenges in controlling the width of fin structures formed by spacer imaging transferring (SIT), which limits the adjustment of the beta ratio and static noise tolerance, as the width cannot be directly controlled by the mask pattern.
Innovation Solution
The introduction of dummy fin structures, with a mandrel pattern of special shape, where more dummy fins are placed around the PG fin structure but not the PD fin structure, allowing for controlled etching to reduce the width of the PG fin structure and maintain the width of the PD fin structure, thereby improving the beta ratio and static noise tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If spacer imaging transferring (SIT) is used to form fin structures, then manufacturing precision is improved, but the ability to adjust fin structure width is lost
Solution Approach 1:
The patent introduces dummy fin structures around the PG fin structure before the etching process. These dummy fins are formed in advance to create a specific etching environment that will selectively reduce the width of the PG fin structure during subsequent etching, while leaving the PD fin structure width unchanged. This preliminary arrangement enables width adjustment capability that was lost with SIT processing.
2Reliability
If the width of PG fin structure is reduced to improve beta ratio, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different treatments to different regions: dummy fin structures are placed only around the PG fin structure, not around the PD fin structure. This localized approach creates different etching conditions for different transistor types, allowing selective width reduction of PG fins to improve beta ratio without uniformly complicating the entire device structure.
Solution Approach 2:
The dummy fin structures are copies of the actual fin structures, using the same formation process (SIT) to create identical geometric patterns. These copy structures serve as etching references that influence the etching behavior of adjacent real fins, enabling width control through pattern replication rather than direct manipulation.
3Reliability
If more dummy fins are placed around PG fin structure, then static noise tolerance is improved, but area occupation increases
Solution Approach 1:
The patent uses a specific number of dummy fin structures (excessive action) around the PG fin structure to ensure sufficient etching reflection and adequate width reduction. This partial application of the dummy fin concept—only around PG fins and not PD fins—achieves the necessary static noise margin improvement while limiting the area penalty to only where it provides benefit.
Data Source
AI summary
The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.