Ferroelectric Back-Gate Transistor Memory for Low-Power Data Retention

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving low power consumption, long-term data retention, and high reliability, especially in neuromorphic circuits that require efficient processing and memory functions.

Innovation Solution

A semiconductor device comprising a first transistor, a second transistor, and a capacitor, where the first transistor has a ferroelectric gate insulating layer for the back gate, allowing it to retain a potential in an off state, and the capacitor changes this potential based on supplied data, enabling efficient data retention and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If a conventional transistor structure is used, then the device complexity is low, but the data retention time is short and power consumption is high

Engineering Contradiction:
Improvedata retention timeVSAvoidpower consumption
Core Design Contradiction:
Duration of action of moving objectVSUse of energy by moving object

Solution Approach 1:

The patent introduces a ferroelectric gate insulating layer that changes the electrical parameters of the transistor by utilizing ferroelectric polarization. This allows the transistor to retain data for long periods without power consumption by maintaining a stable polarization state that preserves the stored information.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure combining ferroelectric material with gate insulating layer. This composite material approach enables both long-term data retention through ferroelectric properties and controlled power consumption by integrating the ferroelectric layer into the existing transistor architecture.

Inventive Principle:
Principle #40Composite materials

2Duration of action of moving object

If a ferroelectric gate insulating layer is introduced, then data retention time increases, but the device complexity increases

Engineering Contradiction:
Improvedata retention timeVSAvoiddevice structure complexity
Core Design Contradiction:
Duration of action of moving objectVSDevice complexity

Solution Approach 1:

The ferroelectric gate insulating layer serves multiple functions simultaneously: it acts as the gate insulator, provides data storage capability through polarization retention, and enables low-power operation. This multi-functionality reduces the need for separate storage components, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the gate insulating layer function with the data storage function by integrating the ferroelectric material directly into the gate structure. This combination eliminates the need for separate storage elements and reduces overall device complexity despite adding ferroelectric functionality.

Inventive Principle:
Principle #5Merging (Combining)

3Use of energy by moving object

If the first transistor retains potential in off state, then power consumption decreases, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvepower consumptionVSAvoidferroelectric layer deposition precision
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent utilizes changes in deposition parameters and thermal processing conditions to achieve the desired ferroelectric properties. By optimizing these parameters, the manufacturing process can produce consistent ferroelectric layers with the required precision for reliable data retention without excessive complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed semiconductor device achieves low power consumption, long-term data retention, and high reliability by utilizing ferroelectric materials in the gate insulating layer and capacitors, which enhance the device's ability to manage and process data efficiently.

Implementation Method 1

A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data supplied to the second back gate through the first transistor.

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

The capacitor has a function of changing the first potential retained in the second back gate to a second potential in accordance with a potential change caused by supply of second data to one electrode of the capacitor.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

The second transistor has a function of making an output current corresponding to a potential of the second back gate flow between a source and a drain of the second transistor. The output current is a current flowing when the second transistor operates in a subthreshold region.

Methodology Applied
Scientific EffectSubthreshold conduction:

Data Source

PatentUS12205625B2Semiconductor device and electronic device
Publication Date: 2025.01.21 SEMICON ENERGY LAB CO LTD
  • US12205625B2 patent drawing
  • US12205625B2 patent drawing
  • US12205625B2 patent drawing

AI summary

A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.