Dual Phase Interpolator Clocking for Low-Jitter Memory Signals
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Solution Overview
Problem
Existing clock signal generators in semiconductor devices face challenges in generating precise internal clock signals with minimal jitter, which affects the reliability of data transmission in volatile memory devices.
Innovation Solution
A clock signal generator comprising an internal signal generator, a first phase interpolator, a second phase interpolator, and a selector, which generate and interpolate internal signals to produce an internal clock signal with adjustable phase differences, reducing jitter by selectively outputting interpolation signals based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single phase interpolator is used to generate internal clock signals, then the circuit complexity is low, but the jitter reduction capability and phase adjustment precision are insufficient
Solution Approach 1:
The phase interpolator is divided into two separate phase interpolators (first and second), each handling different aspects of phase generation. The first phase interpolator generates intermediate phase signals, while the second phase interpolator refines these signals to achieve the desired phase precision with reduced jitter.
Solution Approach 2:
The circuit employs dynamic selection through a selector that chooses between different interpolation paths based on control signals. This dynamic approach allows the system to adaptively select the optimal phase signal, improving precision while managing complexity through conditional operation.
2Reliability
If multiple interpolation paths are added to reduce jitter, then the jitter reduction capability improves, but the device complexity increases
Solution Approach 1:
The jitter reduction is achieved by segmenting the interpolation function into two distinct phase interpolators, each contributing to noise and jitter filtering. This segmentation allows the system to achieve better jitter performance without requiring a single overly complex interpolator.
Solution Approach 2:
The selector acts as an intermediary that manages the outputs from multiple interpolation paths. By selectively combining or choosing between signals from the first and second phase interpolators, the system achieves jitter reduction while maintaining manageable circuit complexity through controlled signal integration.
Data Source
AI summary
Provided are a digital phase interpolator, a clock signal generator, and a volatile memory device including the clock signal generator. The clock signal generator includes an internal signal generator configured to generate a first internal signal and a second internal signal, which mutually have a phase difference, based on an external clock signal, a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal and generate a first interpolation signal, a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal and generate a second interpolation signal, and a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal and output the selected interpolation signal as an internal clock signal.