Latch-Assisted Data Receiver for Faster, Accurate Input Sensing
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Solution Overview
Problem
Memory devices face challenges in maintaining operation speed due to input receivers' inability to accurately interpret input data, leading to potential crashes or abnormal operation.
Innovation Solution
A data receiving circuit comprising a data input circuit, a latch circuit, and a current source, along with transistors and an equalizer, is designed to enhance signal interpretation by providing a current to the latch circuit, improving the circuit's response time and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If input receivers are used to receive input signals in memory devices, then data reception function is provided, but operation speed becomes insufficient and accuracy margin decreases
Solution Approach 1:
The data reception function is divided into two independent circuits: a data input circuit for receiving input signals and a latch circuit for latching data. This segmentation allows each circuit to be optimized independently, with the latch circuit providing enhanced speed and accuracy through dedicated latch transistors and current sources, resolving the contradiction between overall operation speed and data interpretation reliability.
Solution Approach 2:
The latch circuit acts as an intermediary between the data input circuit and the rest of the memory device. It receives processed signals from the data input circuit, performs accurate latching with enhanced speed characteristics, and then provides the latched data to subsequent circuits. This intermediary function isolates the speed-critical latching operation from the input reception, allowing optimization of both stages.
2Productivity
If input receivers operate at high speeds, then operation speed improves, but the margin to correctly determine input data becomes small
Solution Approach 1:
The latch circuit performs preliminary latching of the input data before it is passed to subsequent processing stages. By capturing and stabilizing the data early in the reception process, the circuit ensures that high-speed operation does not compromise accuracy, as the latched data serves as a stable reference for further processing.
Solution Approach 2:
The invention introduces dedicated current sources for the latch transistors that can be independently controlled from the data input circuit current. This parameter change allows optimization of the latch circuit's switching speed and signal levels separately, enabling high-speed operation with sufficient noise margins and accuracy by adjusting current parameters specifically for the latching stage.
Data Source
AI summary
A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.