Memory Bit Line Loop Testing for Short and Open Defect Screening
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Solution Overview
Problem
The increasing complexity of integrated circuits leads to longer testing times and higher costs, with high failure rates and low yield rates during bit line testing in memory devices, indicating defects in the wafer fabrication process, necessitating improved test efficiency.
Innovation Solution
A method for testing memory devices by measuring resistance and current/voltage values in conductive loops formed by bit lines, identifying short circuits or open circuits through specific test patterns, and evaluating reliability, with integrated circuit layout design and manufacturing systems supporting these tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test methods are implemented to improve test efficiency, then test coverage and reliability are improved, but testing time and cost increase significantly
Solution Approach 1:
The patent segments the bit line testing into multiple independent test patterns (first test pattern for first bit lines, second test pattern for second bit lines). Each test pattern can be executed separately, allowing parallel processing and reducing total testing time while maintaining comprehensive coverage through multiple segmented test methods.
Solution Approach 2:
The patent introduces a time dimension by implementing sequential test patterns where first bit lines are tested with a first test pattern and second bit lines are tested with a second test pattern. This dimensional approach allows multiple test methods to be executed in a structured sequence, improving reliability without proportionally increasing total test time.
2Reliability
If multiple test methods are implemented to improve test efficiency, then defect detection capability is improved, but testing cost increases
Solution Approach 1:
By segmenting the testing process into distinct test patterns for different bit lines, the patent enables cost-effective parallel execution of multiple test methods. Each segmented test can be performed with dedicated resources, reducing overall testing cost while maintaining high defect detection capability through comprehensive coverage.
Solution Approach 2:
The patent changes test parameters by using different test patterns (first test pattern vs. second test pattern) that can be configured based on specific bit line requirements. This parameter flexibility allows optimization of testing cost by selecting appropriate test patterns for different defect detection needs without uniformly applying all possible test methods.
3Reliability
If comprehensive testing is performed to identify all defects, then yield rate is improved, but production time increases
Solution Approach 1:
The patent segments comprehensive testing into manageable test patterns that can be executed in parallel for different bit lines. This segmentation allows the system to achieve high yield rates through thorough defect identification while reducing production time by processing multiple bit lines simultaneously rather than sequentially.
Solution Approach 2:
The patent implements continuous testing through sequential activation of different test patterns. While first bit lines are being tested with the first test pattern, second bit lines can simultaneously undergo the second test pattern, ensuring continuous productive action throughout the manufacturing process and eliminating idle time.
4Measurement precision
If bit line testing is performed with high precision, then defect identification accuracy is improved, but testing complexity increases
Solution Approach 1:
The patent segments the complex testing procedure into distinct, manageable test patterns with specific measurement objectives. Each test pattern targets specific bit lines and defect types, simplifying the overall testing complexity while maintaining high measurement precision through focused, systematic measurement approaches.
Solution Approach 2:
The patent implements preliminary action by pre-defining specific test patterns before actual testing begins. These pre-configured patterns include predetermined measurement sequences and criteria, which simplifies the testing process execution and reduces on-the-fly complexity while ensuring high defect identification accuracy through standardized procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances test efficiency by accurately identifying defects in bit lines, improving yield and reducing production costs by screening out failed devices before shipping.
Implementation Method 1
measuring resistance and current/voltage values in conductive loops formed by bit lines
Data Source
AI summary
A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.