4CPP SRAM Layout for Reduced Bit Line Capacitance
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Solution Overview
Problem
Existing SRAM devices with 4CPP architecture face high bit line capacitance due to the arrangement of even-numbered and odd-numbered rows along the lengthwise direction of bit lines, leading to increased bit line capacitive loading and undesirable routing lengths.
Innovation Solution
The memory array is designed with a pseudo-reduced 4CPP architecture where even-numbered and odd-numbered rows are alternately arranged along the word lines, reducing the effective contacted polysilicon pitch and incorporating multiple word lines into each word line set to minimize bit line length and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If even-numbered and odd-numbered rows are arranged along the lengthwise direction of bit lines in conventional 4CPP architecture, then the memory array can be fully utilized, but the bit line length increases leading to high bit line capacitance
Solution Approach 1:
The patent reorganizes the memory array layout by alternating even-numbered and odd-numbered rows along the word line direction instead of the bit line direction. This dimensional reorganization reduces the bit line length while maintaining full memory array utilization through a pseudo-reduced 4CPP architecture that incorporates multiple word lines into each word line set.
2Length of moving object
If bit line length is reduced to lower capacitance, then bit line capacitive loading decreases, but memory array utilization may be compromised
Solution Approach 1:
The patent segments the word lines into multiple word line sets, with each set containing multiple individual word lines. This segmentation allows the memory array to be accessed through multiple pathways, reducing the bit line length required to access each memory cell while maintaining full utilization of the memory array capacity.
3Ease of manufacture
If conventional 4CPP architecture is used, then manufacturing is straightforward, but bit line capacitive loading is high
Solution Approach 1:
The patent modifies the architectural parameters of the 4CPP structure by implementing a pseudo-reduced configuration where multiple word lines are incorporated into each word line set. This parameter change reduces the effective contacted polysilicon pitch and bit line length, thereby reducing bit line capacitive loading while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
A semiconductor device includes a first memory cell in a 4CPP architecture; a second memory cell formed in the 4CPP architecture and physically disposed next to the first memory cell along a first lateral direction; a first word line extending along the first lateral direction and operatively coupled to the first memory cell; a second word line extending along the first lateral direction and operatively coupled to the first memory cell; a third word line extending along the first lateral direction and operatively coupled to the second memory cell; a fourth word line extending along the first lateral direction and operatively coupled to the second memory cell; a first bit line extending along a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first memory cell; and a second bit line extending along the second lateral direction and operatively coupled to the second memory cell.