CMOS Active Inductor Circuit for High-Speed Memory Receivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory interface devices face challenges in optimizing power, performance, and area (PPA) at high data rates, particularly with GDDR6 SDRAM, due to power supply induced jitter and intersymbol interference, and traditional equalization schemes like DFE are not suitable for random data patterns.
Innovation Solution
The implementation of active inductor circuits with MOS transistors and capacitors in amplifier designs to enhance timing margin and bandwidth, allowing for accurate data detection without continuous DFE training, thereby improving the receiver's ability to handle high-speed data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional equalization schemes like DFE are used, then timing margin is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the essential equalization function from complex DFE circuits and implements it through a simplified active inductor circuit with controlled inductance. This active inductor provides the necessary timing margin improvement without requiring the complex feedback and adaptation mechanisms of traditional DFE, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The patent changes the inductance parameter of the active inductor dynamically based on process, voltage, and temperature (PVT) conditions. By adjusting the inductance value through control circuits that sense PVT variations, the system maintains optimal timing margin across different operating conditions without requiring complex adaptive equalization algorithms, thus improving reliability while controlling device complexity.
2Reliability
If traditional equalization schemes like DFE are used, then timing margin is improved, but power consumption increases
Solution Approach 1:
The patent extracts the core equalization functionality from power-hungry DFE circuits and implements it through an energy-efficient active inductor. This active inductor provides timing margin improvement with significantly lower power consumption by eliminating the need for continuous feedback sampling and adaptation operations that consume substantial power in traditional DFE implementations.
Solution Approach 2:
The patent implements dynamic inductance adjustment through PVT compensation circuits that consume minimal power compared to full DFE operation. The control circuits sense process, voltage, and temperature variations and adjust the inductor parameters accordingly, maintaining optimal timing margin across operating conditions with fraction of the power required by traditional adaptive equalization schemes.
3Measurement precision
If bandwidth is increased to handle high data rates, then data detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic active inductor circuit where the inductance value can be adjusted in real-time based on operating conditions and signal characteristics. This dynamic adjustment allows the circuit to optimize bandwidth for accurate data detection only when needed, rather than maintaining high bandwidth continuously, thereby achieving high data detection accuracy at high data rates with reduced average power consumption compared to static high-bandwidth designs.
Data Source
AI summary
A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.