Three-Element ReRAM Cell Layout for Disturb-Resistant Endurance
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Solution Overview
Problem
ReRAM memory cells formed from pairs of back-to-back devices are susceptible to failure due to potential short circuits or inability to switch off, leading to endurance issues in FPGA devices, particularly in multiplexers and look-up tables, where unpredictable logic level voltages can cause disturb phenomena.
Innovation Solution
Incorporating a third ReRAM device in series with two back-to-back ReRAM devices to act as a redundant element, reducing stress on each device to 0.4V, thereby mitigating the risk of failure and ensuring continued functionality even if one device fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pair of ReRAM devices are connected in back-to-back orientation, then the device can avoid disturb during logic switching, but the device is susceptible to failure due to short circuits or inability to switch off
Solution Approach 1:
The memory cell is segmented into three ReRAM devices instead of two, with each device experiencing reduced voltage stress. This segmentation distributes the voltage burden, reducing stress on each individual device to 0.4V and mitigating failure risks from short circuits or switching failures.
Solution Approach 2:
The third ReRAM device acts as a redundant element that cushions against potential failures. If one device fails to erase or shorts, the remaining two devices can still maintain the memory cell functionality, providing beforehand protection against endurance issues.
2Ease of operation
If voltage potential is applied across ReRAM devices to program or erase, then the conductive path can be formed or eliminated, but the stress on individual devices increases failure risk
Solution Approach 1:
The voltage stress during programming and erasing is segmented across three devices instead of two. Each device experiences reduced voltage stress (0.4V), which maintains the programming and erasing capability while reducing the risk of failure from excessive stress.
Solution Approach 2:
The voltage parameter is changed by distributing it across three devices, reducing the voltage stress on each individual device. This parameter change maintains operational capability while improving reliability by reducing stress-induced failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The addition of a third ReRAM device enhances the endurance of ReRAM memory cells by reducing the stress on individual devices, thereby minimizing the likelihood of failure and maintaining reliable operation in FPGA circuits.
Implementation Method 1
a voltage potential placed across the two terminals of the device causes metal ions from the ion source layer to migrate into the solid electrolyte layer to form a conductive path
Implementation Method 2
applying a voltage potential across the two terminals of the device opposite in polarity to the potential that was used to program the device causes the metal ions to migrate back into the ion source layer
Data Source
AI summary
A resistive random access memory cell includes three resistive random access memory devices, each resistive random access memory device having an ion source layer and a solid electrolyte layer. The first and second resistive random access memory devices are connected in series such that either both ion source layers or both solid electrolyte layers are adjacent to one another. A third resistive random access memory device is connected in series with the first and second resistive random access memory devices.