Cross FET SRAM Cell Layout for Dense 6T Bit Cell Routing
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Solution Overview
Problem
Current semiconductor chip design techniques face challenges such as capacitive coupling, electro migration, short channel effects, and processing yield issues, which affect device placement and signal routing, leading to delays in design completion and increased time to market.
Innovation Solution
The use of vertically stacked gate all around (GAA) transistors with an orthogonal orientation between the top and bottom transistors, known as Cross FETs, in memory bit cells to reduce planar area consumption, enhance performance, and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If standard planar transistor layouts are used in memory bit cells, then routing and connection are simpler, but on-die area consumption is larger
Solution Approach 1:
The patent transitions from planar (2D) transistor layouts to vertically stacked (3D) transistor configurations. By stacking transistors in the vertical dimension, the memory bit cell achieves higher density and reduced on-die area consumption while maintaining all necessary electrical connections through carefully designed via structures that penetrate the stacked layers.
Solution Approach 2:
The patent implements nested transistor structures where transistors are stacked one on top of another in a hierarchical arrangement. The bottom transistor is nested within the same footprint as the top transistor, allowing both devices to occupy the same planar area while maintaining distinct electrical pathways through vertical separation and selective connectivity.
2Productivity
If more components are placed on the same die to increase functionality, then chip performance improves, but signal congestion and routing complexity increase
Solution Approach 1:
By stacking transistors vertically, the patent creates additional routing dimensions through multiple metal layers and via structures. This vertical dimensionality allows signals to bypass congested planar routing paths and establishes direct vertical connections between stacked devices, reducing overall routing complexity despite increased component density.
3Area of stationary object
If vertically stacked transistors are used to reduce area, then on-die area consumption decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary structures such as insulating layers, sacrificial materials, and alignment markers between stacked transistors. These intermediaries facilitate precise alignment during manufacturing by providing physical references and isolation layers that guide the placement of subsequent layers, thereby reducing the overall precision burden on the fabrication process.
4Reliability
If manual full-custom designs are used to optimize performance, then design quality improves, but design cycle time increases
Solution Approach 1:
The patent segments the memory bit cell design into standardized modular units with predefined vertical stacking configurations. This segmentation allows design automation tools to efficiently assemble optimized bit cells from pre-characterized building blocks, capturing the benefits of manual optimization while enabling automated design flow and reducing overall design cycle time.
Data Source
AI summary
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.