Memory Cell Line Switching to Isolate Idle Bit Lines
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Solution Overview
Problem
Existing memory devices have high power consumption due to idle bit lines being activated during read/write operations, which is inefficient and increases energy usage.
Innovation Solution
The memory device incorporates column and row switches controlled by word lines to selectively connect only the necessary bit lines to memory cells during operations, reducing unnecessary power consumption by isolating unrequired bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are coupled to memory cells during read/write operations, then data transmission is simplified and reliable, but power consumption increases due to idle bit lines
Solution Approach 1:
The patent segments the bit lines into multiple groups, with each group independently coupled to a specific memory cell group. This segmentation allows only the bit line groups corresponding to active memory cells to be activated during read/write operations, while other bit line groups remain inactive, thereby reducing overall power consumption while maintaining reliable data transmission for the selected cells.
2Use of energy by moving object
If column and row switches are added to selectively connect bit lines to memory cells, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the control functions of column and row switches into a unified control mechanism. Column switches are controlled by column selection signals and row switches are controlled by row selection signals, with both working together to select specific memory cells. This merging approach allows selective activation of bit lines through coordinated row and column decoding, reducing power consumption while managing device complexity through systematic control integration.
Data Source
AI summary
A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.