Differential Input Buffer Offset Cancellation Through Current Balancing
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Solution Overview
Problem
In semiconductor devices with differential input buffers, matching the characteristics of transistors on the input and reference sides is challenging, leading to difficulties in accurately adjusting input offsets.
Innovation Solution
A circuit configuration using data latch circuits with DFE circuits and current control circuits, adjusted by down-code and up-code signals, to synchronize and equalize current flow, thereby canceling input offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a differential input buffer is used to compare input signal levels with reference potential, then the input buffer can provide differential signaling benefits, but it becomes difficult to match transistor characteristics between input side and reference side circuits
Solution Approach 1:
The patent applies dynamics by making the reference side transistor characteristics adjustable through tap selection circuits. Instead of fixed matching, the reference transistors can be dynamically reconfigured to match the input side transistor characteristics under different operating conditions, process variations, and temperature ranges, resolving the contradiction between maintaining differential signaling performance and achieving precise transistor matching
Solution Approach 2:
The patent changes the parameters of the reference side transistors by selecting different tap points that correspond to different transistor sizes or configurations. This allows the reference side to be adjusted to match the input side transistor characteristics, thereby resolving the manufacturing precision issue while maintaining differential signaling performance
2Measurement precision
If transistor characteristics are required to match between input side and reference side, then input offset accuracy can be improved, but the device complexity increases due to additional matching and adjustment circuits
Solution Approach 1:
The patent segments the reference side into multiple tap selection circuits, each corresponding to different transistor characteristic configurations. This segmentation allows selective activation of specific reference transistors to match the input side, achieving high input offset accuracy without requiring all reference transistors to be permanently configured, thereby reducing overall device complexity
Solution Approach 2:
The patent introduces tap selection circuits as intermediary elements between the reference transistors and the differential input buffer. These intermediary circuits enable dynamic selection and configuration of reference transistor characteristics, simplifying the matching process while maintaining high input offset accuracy without direct complex interconnections
3Device complexity
If fixed transistor characteristics are used in differential input buffer, then device complexity is reduced, but the ability to adjust input offsets under varying operating conditions is limited
Solution Approach 1:
The patent transforms the static, fixed transistor characteristics into dynamic, adjustable characteristics through tap selection circuits. The reference side can adapt its transistor configuration based on operating conditions, process variations, and temperature changes, providing versatility and adaptability while maintaining relatively simple circuit architecture through selective activation of tap points
Data Source
AI summary
An example apparatus includes: first and second inverters cross-coupled to each other, a first transistor coupled between the first and third circuit nodes; a second transistor coupled between the second and fourth circuit nodes; a plurality of third transistors coupled in parallel between the third circuit node and the second power line; and a plurality of fourth transistors coupled in parallel between the fourth circuit node and the second power line. When the control code signal indicates a first value: at least one of the plurality of third transistors is brought into an OFF state; remaining one or ones of the plurality of third transistors are brought into an ON state; at least one of the plurality of fourth transistors is brought into an OFF state; and remaining one or ones of the plurality of fourth transistors are brought into an ON state.