Oxide Semiconductor DRAM Channel Contacts for Low Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of DRAM devices with a 1T-1C structure increases leakage current through the channel area, necessitating a reduction in contact resistance while maintaining reduced dimensions.
Innovation Solution
The use of an oxide semiconductor material for the active semiconductor layer, combined with ion-implanted dopants in the contacts, reduces leakage current and contact resistance by enhancing carrier mobility and reducing resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DRAM device size is reduced through miniaturization, then integration density is improved, but leakage current through the channel area increases
Solution Approach 1:
The patent changes the material parameter of the channel layer from conventional semiconductor materials to oxide semiconductor materials, which have inherently lower leakage current characteristics. This material parameter change enables the device to maintain miniaturization benefits while suppressing leakage current through the channel area.
2Object-generated harmful factors
If oxide semiconductor material is used for the channel layer, then leakage current is reduced, but contact resistance increases
Solution Approach 1:
The patent applies local quality by forming a contact hole that penetrates through the oxide semiconductor layer to reach the underlying substrate or conductive layer. This creates a localized conductive path at the contact region, reducing contact resistance without affecting the leakage current characteristics of the main channel area.
Solution Approach 2:
The contact hole acts as an intermediary structure that bridges the oxide semiconductor channel layer and the conductive substrate. By providing this intermediate conductive pathway, the contact resistance is reduced while maintaining the insulating properties of the oxide semiconductor material in the channel region.
3Reliability
If a contact hole is formed to reduce contact resistance, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the contact hole formation with the existing oxide semiconductor layer deposition and patterning processes. The contact hole is formed as an integral part of the channel layer structure, combining multiple functions into a single manufacturing sequence and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves reduced leakage current and contact resistance, maintaining excellent electrical characteristics and integration density.
Implementation Method 1
The use of an oxide semiconductor material for the active semiconductor layer, combined with ion-implanted dopants in the contacts, reduces leakage current and contact resistance by enhancing carrier mobility and reducing resistivity
Implementation Method 2
combined with ion-implanted dopants in the contacts, reduces leakage current and contact resistance
Implementation Method 3
enhancing carrier mobility and reducing resistivity
Data Source
AI summary
A semiconductor device includes: a bit line; an active semiconductor layer on the bit line, having a first portion extending in a vertical direction and a second portion connected to the first portion and extending in a horizontal direction, including an oxide semiconductor; a word line on a side wall of the active semiconductor layer; a gate insulating layer between the active semiconductor layer and the word line; a first contact on the active semiconductor layer, having a bottom at a level lower than a top surface of the word line and a top at a level higher than the top surface of the word line, including an oxide semiconductor containing a first dopant; a second contact adjacent to the second portion of the active semiconductor layer on the bit line and including an oxide semiconductor containing a second dopant; and a landing pad on the first contact.