Ferroelectric 3T Memory Gates for Faster Switching and Retention
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Solution Overview
Problem
Conventional 3T DRAM transistors with non-ferroelectric gate oxides have limited switching speeds and shorter data retention times due to high subthreshold swing and gate leakage.
Innovation Solution
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization and negative gate capacitance, respectively, enhancing data retention and switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional non-ferroelectric gate oxides are used in 3T DRAM transistors, then the device structure is simpler and easier to manufacture, but the switching speed is limited and data retention time is short
Solution Approach 1:
The patent employs composite gate structures combining ferroelectric materials (such as hafnium zirconium oxide) with conventional dielectric materials. This composite approach enables the transistor to achieve both fast switching speeds through ferroelectric polarization effects and acceptable manufacturability by integrating with existing CMOS fabrication processes. The multi-layer gate structure includes ferroelectric layers, barrier layers, and dielectric layers that work together to resolve the contradiction between performance improvement and manufacturing complexity.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate oxide material by transitioning from conventional non-ferroelectric materials to ferroelectric materials with specific properties (such as HfZrO4 with controlled composition ratios). By adjusting material composition parameters (e.g., Zr content, oxygen content) and structural parameters (layer thickness, stacking sequence), the patent achieves enhanced switching speed while managing the increased complexity through systematic parameter optimization.
2Duration of action of stationary object
If conventional gate oxides are used, then the manufacturing process is simpler, but data retention time is limited due to gate leakage
Solution Approach 1:
The patent uses composite gate structures with ferroelectric materials that provide non-volatile data storage capability. The ferroelectric layer's remnant polarization maintains data without power, dramatically extending data retention time. The composite structure includes barrier layers and dielectric layers that work together to suppress gate leakage while preserving the ferroelectric effect, thus achieving long data retention without excessive complexity.
Solution Approach 2:
The patent converts the typically harmful gate leakage effect into a beneficial feature by utilizing the ferroelectric material's ability to maintain stable polarization states. The ferroelectric gate structure transforms what would be leakage current in conventional devices into a mechanism for non-volatile data retention, where the polarization state itself represents stored data that persists without power.
3Reliability
If ferroelectric materials are incorporated into gate structures, then data retention time increases and switching speed improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs gate structures that serve multiple functions simultaneously: the ferroelectric layer provides both data storage (non-volatility) and switching functionality, while integrated barrier and dielectric layers provide both electrical isolation and mechanical support. This multi-functionality reduces the need for separate components, thereby managing manufacturing complexity despite the advanced materials used.
Solution Approach 2:
The patent optimizes manufacturing feasibility by carefully controlling material parameters such as deposition temperatures, layer thicknesses, and composition ratios during fabrication. By adjusting these parameters within specific ranges, the patent achieves reliable ferroelectric film formation and interface quality that are compatible with existing semiconductor manufacturing capabilities, thus improving ease of manufacture while maintaining enhanced data retention.
4Loss of time
If ferroelectric materials are used in transistors, then write and read times are reduced, but the structural complexity of the transistor increases
Solution Approach 1:
The patent employs composite gate structures where ferroelectric materials enable ultra-fast switching through polarization switching mechanisms, dramatically reducing write and read times. The composite structure integrates ferroelectric layers with conventional transistor components, allowing the fast switching benefit to be achieved while minimizing the impact on overall transistor structure and surrounding circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of ferroelectric materials in 3T DRAM transistors increases data retention times and switching speeds, reducing write and read times, and potentially making the memory nonvolatile.
Implementation Method 1
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization and negative gate capacitance, respectively
Implementation Method 2
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization and negative gate capacitance, respectively
Data Source
AI summary
A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.