Vertical 2-Transistor Memory Cell With Separate Read/Write Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, and require complex access line management to prevent read disturb and maintain proper transistor operation.
Innovation Solution
The memory device employs separate access lines for each memory cell to independently control transistors during read and write operations, reducing the need for high threshold voltages in write access transistors and providing built-in shield structures to prevent transistor disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used to increase storage density, then device storage density improves, but physical limitations and fabrication constraints prevent further size reduction
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D structure where the channel extends in the vertical direction through stacked gate electrodes. This dimensional change allows continued scaling of storage density without further reducing the lateral footprint of each memory cell, overcoming physical limitations of conventional 2D scaling.
Solution Approach 2:
The patent implements nested gate structures where multiple gate electrodes (first gate, second gate, third gate) are stacked vertically around a common channel region. This nesting arrangement allows multiple control elements to occupy the same lateral space, increasing functional density without proportionally increasing device area.
2Device complexity
If the same access line is used to control multiple access transistors, then device complexity is reduced, but threshold voltage requirements become more stringent to prevent read disturb
Solution Approach 1:
The patent divides the single shared access line into separate access lines for different transistor groups. Specifically, first and second access lines control first and second access transistors independently, while a third access line controls third and fourth access transistors. This segmentation allows independent voltage control, preventing read disturb without requiring complex threshold voltage matching across all transistors.
Solution Approach 2:
The patent applies different threshold voltage characteristics to different access transistors by providing them with separate access lines. This allows each transistor group to be optimized locally for its specific function (read vs. write operations) rather than requiring all transistors to meet the same stringent threshold voltage requirements.
3Area of stationary object
If memory cell size is reduced to increase storage density, then device area is reduced, but fabrication constraints and physical limitations are exceeded
Solution Approach 1:
The patent moves critical dimensions from the lateral plane to the vertical dimension. The channel length is defined by vertical stacking height rather than lateral distance, and gate control is achieved through vertical field effects. This allows continued miniaturization of device area while maintaining manufacturability through vertical fabrication processes that are less constrained by lateral resolution limits.
Solution Approach 2:
The patent employs dynamically controllable threshold voltages through separate access lines that can be independently biased. This dynamic control allows the system to adapt transistor characteristics during different operation phases (read vs. write), enabling reliable operation with smaller, more densely packed cells without requiring excessively tight fabrication tolerances.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.