Ferroelectric Memory Bottom Electrodes With Self-Aligned Cavities
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Solution Overview
Problem
Existing manufacturing techniques for ferroelectric memory devices face challenges in maintaining the stability of bottom electrodes due to mechanical stress, which can lead to misalignment or deformation during the manufacturing process.
Innovation Solution
A self-aligned manufacturing technique is employed, where a continuous layer of dielectric material is formed over an assembly with transistors, and an array of cavities is etched to expose contacts. Bottom electrodes are then formed on the sidewalls of these cavities, benefiting from the mechanical support of the dielectric material lattice to reduce stress and improve stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing techniques are used to form bottom electrodes, then the manufacturing process can be completed, but the bottom electrodes experience mechanical stress leading to misalignment or deformation
Solution Approach 1:
The patent forms a sacrificial layer and cavities before forming the bottom electrodes. This preliminary structure provides mechanical support during the electrode formation process, preventing stress-induced deformation. The sacrificial layer is deposited and patterned first, creating a template that guides subsequent electrode formation while providing structural stability.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element between the substrate and the bottom electrodes. This sacrificial layer temporarily provides mechanical support during manufacturing, then is removed to create the final electrode structure. The intermediary structure enables precise electrode formation without direct mechanical stress on the electrodes themselves.
2Reliability
If bottom electrodes are formed with high aspect ratios to achieve desired capacitance, then the storage capacity is improved, but the electrodes become more susceptible to mechanical stress and deformation
Solution Approach 1:
The sacrificial layer and cavity structure are formed before the bottom electrodes, providing a pre-established mechanical framework. This framework supports the high aspect ratio electrodes during formation, preventing the deformation that would normally occur with such slender structures. The preliminary structure enables the electrodes to achieve their final high aspect ratio without compromising dimensional accuracy during manufacturing.
Solution Approach 2:
The patent changes the mechanical parameters of the surrounding structure by forming cavities and using sacrificial materials. This creates a low-stress environment that allows the bottom electrodes to maintain their high aspect ratio geometry. The parameter change in the supporting structure enables the electrodes to achieve the desired capacitance without suffering from stress-induced dimensional changes.
Data Source
AI summary
Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.