Ferroelectric Memory Capacitor Layout to Prevent Electrode Shunting

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Solution Overview

Problem

Existing semiconductor memory technologies face challenges in achieving reliable and efficient non-volatile memory solutions, particularly in preventing shunting and improving device performance in ferroelectric random access memory (FERAM) cells.

Innovation Solution

A 1T-1C memory cell design is implemented, featuring a capacitor with a ferroelectric material sandwiched between a bottom electrode layer and a top electrode layer, where the bottom electrode layer is patterned to be below the spacers, preventing shunting and improving isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bottom electrode layer is positioned at the same level as the spacers, then the capacitor structure is simpler, but shunting occurs between the bottom electrode and contacts

Engineering Contradiction:

Improveprevention of shuntingVSAvoidelectrode positioning complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The bottom electrode layer is positioned in a different vertical dimension (below the spacers) rather than at the same level, creating spatial separation that prevents shunting between the bottom electrode and contacts while maintaining capacitor functionality

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the bottom electrode layer is patterned below the spacers, then isolation is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveisolation effectivenessVSAvoidpattern alignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The bottom electrode layer is patterned below the spacers in advance, establishing isolation boundaries before subsequent manufacturing steps, which prevents shunting pathways from forming while managing precision requirements through proactive design

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the reliability and performance of FERAM cells by reducing errors and improving device performance through effective isolation of the bottom electrode from contacts, thereby preventing shunting.

Implementation Method 1

a first ferroelectric layer over the first electrode

Methodology Applied

Scientific EffectFerroelectric polarization:

Data Source

PatentUS12243573B2Semiconductor devices including ferroelectric memory and methods of forming the same

Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.