Unified Latch Scan Chains for Area-Efficient Memory Test
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Solution Overview
Problem
Conventional semiconductor fabrication designs with embedded scan chains require significant area due to multiple signals and associated circuitry, necessitating a redesign to reduce the area footprint of integrated circuitry.
Innovation Solution
The implementation of latch circuitry that reduces the number of scan-shift chains by unifying scan chains in asynchronous read and write clock domains, merging signals like data, write enable, and read into a single scan chain, and reducing observability latches, thereby achieving area-efficient memory design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional embedded scan chains with full scan flip-flops are used for asynchronous clock design, then testability is maintained, but area footprint increases significantly
Solution Approach 1:
The patent merges multiple scan chains (write data-in, write enable, and read data-out) into a unified scan chain structure. This consolidation reduces the number of separate full scan flip-flops required while maintaining the ability to test all functional paths, thereby reducing area footprint without sacrificing testability.
Solution Approach 2:
The unified scan chain is designed to serve multiple functions: it can capture write data, capture write enable signals, and capture read data outputs within the same structural framework. This multi-functionality eliminates the need for separate dedicated scan chains for each signal type, reducing overall area while preserving comprehensive test coverage.
2Reliability
If multiple scan chains are used to capture different signals in asynchronous clock design, then complete signal coverage is achieved, but device complexity increases
Solution Approach 1:
Multiple separate scan chains for different signals are merged into a single unified scan chain that sequentially captures write data, write enable, and read data outputs. This consolidation reduces device complexity by eliminating redundant chain control logic while maintaining complete signal coverage through systematic capture sequences.
Solution Approach 2:
The unified scan chain employs segmented capture phases that systematically divide the capture process into distinct segments: write data capture, write enable capture, and read data output capture. This segmentation allows complete signal coverage to be achieved through organized phase-based operation rather than requiring parallel complex structures.
3Reliability
If full scan flip-flops are used for each signal in embedded scan chains, then test quality is maintained, but area footprint increases
Solution Approach 1:
The patent combines multiple full scan flip-flop instances into a unified scan chain structure where a single flip-flop serves multiple capture functions across different phases. This merging maintains test quality by ensuring all signals are captured with full scan functionality while reducing the total number of flip-flops required, thereby reducing area footprint.
Solution Approach 2:
The unified scan chain implements a universal capture mechanism that can capture different signal types (write data, write enable, read data) using the same structural elements. This multi-functionality ensures full test quality is maintained across all signals while avoiding the area penalty of having separate dedicated full scan flip-flops for each signal type.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.