Resistor-Array Interface Circuit Without Interlayer ADCs
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Solution Overview
Problem
Existing neural network implementations require analog-to-digital converters (ADCs) between successive layers, which occupy significant chip area and consume power, limiting the efficiency of data processing and transfer.
Innovation Solution
The implementation of neural networks using matrices or arrays of resistors allows for direct analog voltage transfer between layers, omitting the need for ADCs and reducing chip area and power consumption by using resistor arrays and interface circuits to perform data transfer and processing without digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ADCs are used between successive layers of neural network, then data conversion accuracy is improved, but chip area and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the neural network architecture. By directly connecting successive layers of resistor arrays, the system eliminates the need for analog-to-digital conversion, thereby removing the chip area and power consumption overhead associated with ADCs while maintaining computational functionality through pure analog signal processing
Solution Approach 2:
The patent substitutes the mechanical/electronic ADC conversion process with a direct analog signal transmission mechanism. Instead of converting analog signals to digital and back, the system uses voltage signals to directly control current flow through resistor arrays, replacing the ADC conversion mechanism with an analog-multiplication-based computation approach
2Measurement precision
If ADCs are used between successive layers of neural network, then data conversion accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the ADC component from the neural network architecture. By directly connecting successive layers of resistor arrays, the system eliminates the need for analog-to-digital conversion, thereby removing the chip area and power consumption overhead associated with ADCs while maintaining computational functionality through pure analog signal processing
Solution Approach 2:
The patent substitutes the mechanical/electronic ADC conversion process with a direct analog signal transmission mechanism. Instead of converting analog signals to digital and back, the system uses voltage signals to directly control current flow through resistor arrays, replacing the ADC conversion mechanism with an analog-multiplication-based computation approach
3Measurement precision
If ADCs are used between successive layers of neural network, then data processing accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent enables continuous analog signal flow between successive layers without the interruption of ADC conversion cycles. By maintaining uninterrupted voltage and current signal transmission through directly connected resistor arrays, the system achieves continuous computation operations, eliminating the time delays inherent in sequential ADC conversion processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster processing, reduced chip area, and lower power consumption compared to traditional methods that rely on ADCs, facilitating more efficient data transfer and computation within neural networks.
Implementation Method 1
A first array of resistors is electrically coupled between a plurality of first input conductive lines and a plurality of first output conductive lines. A second array of resistors is electrically coupled between a plurality of second input conductive lines and a plurality of second output conductive lines.
Data Source
AI summary
An integrated circuit includes first and second arrays of resistors, and a plurality of interface circuits. Each resistor in the first array is electrically coupled between a corresponding first input conductive line among a plurality of first or second input conductive lines, and a corresponding first output conductive line among a plurality of first or second output conductive lines. Each resistor in the second array is electrically coupled between a corresponding second input conductive line among a plurality of second input conductive lines, and a corresponding second output conductive line among a plurality of second output conductive lines. Each interface circuit is electrically coupled between a corresponding first output conductive line and a corresponding second input conductive line. Each interface circuit is configured to receive a signal on the corresponding first output conductive line, and apply an analog voltage corresponding to the signal to the corresponding second input conductive line.