DDR4 I/O Driver Topology Without Voltage Shifting Circuits
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Solution Overview
Problem
Conventional DDR4 memory I/O drivers require large circuit areas and compromise bandwidth due to voltage differences between core and I/O power domains, necessitating voltage shifting circuits and cascode transistors that increase complexity and reduce performance.
Innovation Solution
A DDR4 memory I/O driver design that operates in a single power domain, eliminating the need for voltage shifting circuits and cascode transistors, utilizing a pre-driver, pull-up PMOS transistor, and pull-down NMOS transistor circuits to maintain signal integrity and reduce circuit area while enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage shifting circuit and LDO are used to adapt to voltage difference between core power domain and I/O power domain, then voltage compatibility is improved, but circuit area increases
Solution Approach 1:
The patent extracts and removes the voltage shifting circuit and LDO components from the DDR PHY I/O architecture. By operating both the core logic and I/O interface in the same power domain (1.2V for DDR4), the design eliminates the need for voltage conversion infrastructure, thereby reducing circuit area while maintaining voltage compatibility through domain unification
Solution Approach 2:
The patent merges the core power domain and I/O power domain into a single unified power domain. Instead of maintaining separate voltage domains with conversion circuits, the design combines both operations into one domain, eliminating the interface complexity and area overhead associated with voltage shifting and regulation
2Reliability
If cascode PMOS circuit is used to increase withstand voltage, then voltage tolerance is improved, but bandwidth decreases
Solution Approach 1:
The patent removes the cascode PMOS circuit from the I/O driver architecture. Since the entire system operates in a unified 1.2V power domain, the additional voltage tolerance provided by cascode structures is unnecessary. This extraction eliminates the bandwidth limitation imposed by the cascode configuration while sufficient voltage headroom remains available in the unified domain
Solution Approach 2:
The patent changes the voltage domain parameter from multi-domain (with voltage conversion) to single-domain (unified 1.2V), which alters the operating conditions such that cascode transistors are no longer needed for voltage tolerance, thereby enabling direct use of simpler transistor structures that provide higher bandwidth
3Adaptability or versatility
If voltage shifting circuit is used to convert between power domains, then power domain adaptability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the voltage shifting circuit from the system architecture. By designing the DDR PHY I/O to operate natively in the same 1.2V power domain as the core logic, the design removes the entire voltage shifting infrastructure including control logic, thereby reducing device complexity while maintaining operational adaptability through unified domain operation
Solution Approach 2:
The patent applies universality by designing a single power domain that serves both core logic and I/O interface functions. This unified 1.2V domain can handle both computational and interface operations without requiring separate voltage domains or conversion circuits, thereby reducing complexity while maintaining versatility across different operational modes
Data Source
AI summary
The present invention discloses a DDR4 memory I/O driver including a pre-driver, a pull-up circuit and a pull-down circuit. The pre-driver is coupled between a first high voltage terminal and a low voltage terminal to provide a first and a second pre-driving signals. The pull-up circuit includes: a driving PMOS transistor coupled between a second high voltage terminal and a pull-up resistor, that is coupled to an output pad, to operate according to the first pre-driving signal, in which the second high voltage terminal's voltage is not higher than the first high voltage terminal's voltage. The pull-down circuit includes: a driving NMOS transistor coupled between the low voltage terminal and a cascode NMOS transistor to operate according to the second pre-driving signal; and the cascode NMOS transistor coupled between the driving NMOS transistor and a pull-down resistor, that is coupled to the output pad, to operate according to a bias.